Electrostatic Discharge Protection Device

Abstract

The invention provides an electrostatic discharge protection device. The first power line provides a first reference voltage, and the second power line provides a second reference voltage. The detection circuit generates a detection result according to whether there is electrostatic discharge pressure on the first power line. The first NMOS field effect transistor is coupled between the first power line and a common node, and its gate is a first control terminal. The second NMOS field effect transistor is coupled between the common node and the second power line, and its gate is a second control terminal. The intermediate power line provides an intermediate voltage between the first reference voltage and the second reference voltage. The first switching circuit couples the first control terminal to the intermediate power line or the first power line according to the detection result. The second switching circuit couples the second control terminal to the second power line or the first control terminal according to the detection result.

Description

technical field [0001] The present invention relates to electrostatic discharge (ESD) protection devices, and in particular to electrostatic discharge protection devices that avoid time-dependent dielectric breakdown (TDDB) problems. Background technique [0002] In order to avoid the huge damage that electrostatic discharge may cause to circuit components, an electrostatic discharge protection mechanism is generally provided inside the integrated chip. As far as metal-oxide-semiconductor field-effect transistor circuits are concerned, a typical electrostatic discharge protection mechanism uses a single N-type metal-oxide-semiconductor field-effect transistor (hereinafter referred to as NMOS transistor) as a clamp circuit between two power lines ( clamp circuit). In the case of no ESD stress, the NMOS tube will be in the off state to avoid unnecessary power consumption or affect the normal operation of the internal circuit. Only when one of the power lines has electrostati...

AI Technical Summary

Problems solved by technology

The disadvantage of the ESD protection device 100 is that the diode D used to reduce the voltage to provide protection also constitutes a limitation, allowing the transistor M ESD1 , M ESD2 The highest gate voltage can only reach (VDDH-N*VD), so the discharge efficiency of this clamp circuit is not very ideal

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