Bonding structure and manufacturing method thereof
A manufacturing method and bonding structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as complex implementation and easy-to-appear processes
Inactive Publication Date: 2019-08-16
WUHAN XINXIN SEMICON MFG CO LTD
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Problems solved by technology
At present, this technology is mainly used in the packaging between two wafers. When more wafers need to be stacked and integrated, its implementation becomes very complicated and process problems are prone to occur in manufacturing.
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[0045] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and understandable, the specific implementation manners of the present application will be described in detail below in conjunction with the accompanying drawings.
[0046] In the following description, a lot of specific details are set forth in order to fully understand the application, but the application can also be implemented in other ways different from those described here, and those skilled in the art can do it without violating the content of the application. By analogy, the present application is therefore not limited by the specific embodiments disclosed below.
[0047] Secondly, the present application is described in detail in combination with schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged...
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The application provides a bonding structure and a manufacturing method thereof. Multiple chips arranged in an array are formed on the surfaces of wafers. Each chip includes a device structure, an interconnection structure electrically connected with the device structure, and a first packaging cushion layer electrically connected with the interconnection structure. Each first packaging cushion layer is arranged in the edge region of the corresponding chip. After the bonding and cutting of multiple wafers, chip stacks are obtained, and the first packaging cushion layers in the edge regions of the chips are exposed. Thus, when each packaging substrate is provided with an electrical connecting line and a second packaging cushion layer electrically connected with the electrical connecting line, the first packaging cushion layers of the chip stacks can be electrically connected with the second packaging cushion layers of the packaging substrates. Therefore, the chip stacks can be packaged through the packaging substrates to establish electrical connection, bonding can be realized without forming through holes in the wafers, the manufacturing process is simplified, and the reliability ofthe chips is improved.
Description
technical field [0001] The present application relates to the field of semiconductor devices and its manufacture, in particular to a bonding structure and its manufacturing method. Background technique [0002] With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology has been widely used. It uses wafer-level packaging technology to stack and bond wafers with different functions. This technology has high performance and low cost. Advantages of low cost and high integration. [0003] In the implementation of wafer-level packaging technology, Through Silicon Via (TSV) technology is often used. TSV technology is to form a through hole from the back of the wafer and fill it with conductive material to realize the vertical interconnection between wafers. At present, this technology is mainly applied to the packaging between two wafers. When more wafers need to be stacked and integrated, its implementation becomes very co...
Claims
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IPC IPC(8): H01L21/60H01L21/78H01L23/492H01L23/31
CPCH01L24/29H01L24/83H01L21/78H01L23/3185H01L25/0657H01L25/50H01L2225/06565H01L2225/06551H01L2224/83896H01L2224/29186H01L2224/94H01L2224/33181H01L2224/16237H01L2224/08237H01L2224/95H01L2224/92242H01L2224/0556H01L2224/0384H01L24/05H01L24/94H01L24/95H01L24/80H01L24/08H01L24/32H01L24/73H01L24/92H01L2224/80357H01L2924/05042H01L2924/05442H01L2224/83H01L2224/81H01L2224/80001H01L2924/00012H01L2224/03H01L21/304H01L24/06
Inventor 梁斐曹静胡胜
Owner WUHAN XINXIN SEMICON MFG CO LTD