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High-speed data synchronization circuit and data synchronization method

A synchronous circuit, high-speed data technology, applied in electrical digital data processing, instruments, etc., can solve problems such as increasing clock complexity, achieve small delay, solve synchronization problems, and ensure the effect of settling time

Pending Publication Date: 2019-08-23
BRITE SEMICON SHANGHAI CORP
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Problems solved by technology

This increases the clock complexity

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  • High-speed data synchronization circuit and data synchronization method
  • High-speed data synchronization circuit and data synchronization method
  • High-speed data synchronization circuit and data synchronization method

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Embodiment Construction

[0027] The present invention will be further described below in conjunction with accompanying drawing.

[0028] see figure 1 , the high-speed data synchronization circuit of the present invention includes a serial-to-parallel conversion circuit 1 and a phase adjustment circuit 2 .

[0029] The serial-to-parallel conversion circuit 1 uses an analog circuit to realize serial transmission to parallel transmission. Specifically, the serial-to-parallel conversion circuit is provided with: a clock differential input terminal, a data differential input terminal, an 8-divided clock output terminal, and a serial-to-parallel signal output terminal. figure 1 Among them, RX_CP / RX_CN represents the differential input of the high-speed clock, RX_DP / RX_DN represents the differential input of the high-speed data, the data frequency is 2.5Gbps, CLK_HS is the 8-divided clock of the clock differential input RX_CP / RX_CN, and DATA_HS is the 8-bit string The parallel signals, CLK_HS and DATA_HS a...

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Abstract

The invention discloses a high-speed data synchronization circuit and a data synchronization method, and the synchronization circuit comprises a serial-parallel conversion circuit which utilizes an analog circuit to realize conversion from serial transmission to parallel transmission; and a phase adjusting circuit which is connected with the serial-parallel conversion circuit and is used for realizing data and clock phase adjustment by utilizing a digital circuit. Under the condition that the clock delay unit is not dynamically adjusted, the final delay unit of the data is calculated by increasing and decreasing the data end delay unit, the good phase of the data and the clock is achieved, and the synchronization problem of MIPI RX high-speed data is solved with small delay.

Description

technical field [0001] The invention relates to the technical field of data synchronization. Background technique [0002] MIPI (Mobile Industry Processor Interface) is a high-speed interface. When the data frequency exceeds 1.5Gbps, the MIPI protocol requires the adjustment of the data and clock phase difference. The existing high-speed data synchronization technology is generally realized by separately adjusting the delay unit of the data and the clock. When the clock delay unit is adjusted, the internal circuit needs to have a clock that does not follow the clock delay unit, which is used as an internal Operation of sequential logic. This increases clock complexity. Contents of the invention [0003] The purpose of the present invention is to overcome the defects of the prior art and provide a high-speed data synchronization circuit and a corresponding data synchronization method, and solve the synchronization problem of MIPI RX (receiver) high-speed data with a small...

Claims

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Application Information

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IPC IPC(8): G06F13/42G06F13/38
CPCG06F13/423G06F13/4291G06F13/387G06F2213/3852
Inventor 王亮
Owner BRITE SEMICON SHANGHAI CORP
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