A multi-level unit magnetic storage structure and its reading and writing method
A storage structure and magnetic storage technology, applied in information storage, static memory, digital memory information, etc., can solve problems such as deterioration of read and write performance, reduce the occurrence of invalid writing, simplify writing steps, and increase storage density Effect
Active Publication Date: 2021-03-09
BEIHANG UNIV
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[0006] Aiming at the problem that the reading and writing performance of the traditional multi-level unit magnetic storage structure is further deteriorated when it is stacked to three bits mentioned in the above background, the present invention discloses a multi-level unit magnetic storage structure and its reading and writing method
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[0058] The substantive features of the present invention are further described with reference to the accompanying drawings. Detailed exemplary embodiments are disclosed herein, specific structural and functional details thereof are merely representative for purposes of describing exemplary embodiments, therefore, the invention may be embodied in many alternative forms and should not be construed To be limited only to the exemplary embodiments set forth herein, all changes, equivalents, and alternatives falling within the scope of the invention should be covered. Additionally, well-known elements, devices and subcircuits of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the embodiments of the invention.
[0059] Figure 1A , B is a schematic diagram of a continuous MLC structure and a corresponding TLC structure in the prior art.
[0060] like Figure 1A As shown, the continuous MLC is formed by stacking two magnet...
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The invention discloses a multi-level unit magnetic storage structure and a reading and writing method thereof. The storage unit consists of vertically stacked strong spin-orbit coupling materials, a first magnetic tunnel junction, a second magnetic tunnel junction, and a third magnetic tunnel junction from bottom to top. The magnetic tunnel junction and the first electrode, the two ends of the strong spin-orbit coupling material are coated with the second electrode and the third electrode; the shape of the bottom surface of the first magnetic tunnel junction is contained in the upper surface of the strong spin-orbit coupling material, and the third magnetic The shape of the bottom surface of the tunnel junction is contained in the upper surface of the second magnetic tunnel junction, and the shape and size of the upper surface of the first magnetic tunnel junction are exactly the same as the bottom surface of the second magnetic tunnel junction; the free layer of the first magnetic tunnel junction and the strong spin The track coupling materials are in contact; the relative positions of the free layer and the reference layer of the second and third magnetic tunnel junctions are the same as those of the first magnetic tunnel junction. By improving the unit structure and designing a corresponding reading and writing method, the present invention can reduce inter-level interference, simplify the writing steps and optimize the reading performance of the device while increasing the storage density.
Description
【Technical field】 [0001] The invention belongs to the technical field of spin memory, and in particular relates to a multi-level unit magnetic storage structure and a reading and writing method thereof, which are used to realize high-density storage. 【Background technique】 [0002] Magnetic random access memory (MRAM) based on electron spin has the advantages of fast access speed, strong radiation resistance and non-volatility, and is regarded as the most potential next-generation memory technology. The core device of the MRAM memory unit is the Magnetic Tunnel Junction (MTJ). Due to the limitations of the process and magnetic anisotropy, the current MTJ occupies a large area, resulting in low MRAM storage density. Although in recent years, perpendicular magnetic anisotropy MTJs have been used to construct MRAM, which has increased the storage density, it barely reaches the level of Gb capacity. [0003] In contrast, NAND flash technology uses a multi-level cell structure t...
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IPC IPC(8): H01L27/22H01L43/08H01L43/12G11C11/15H10N50/01H10N50/10
CPCG11C11/15H10B61/00H10N50/01H10N50/10G11C11/5607G11C11/161G11C11/1675
Inventor 徐岩松王昭昊吴比赵巍胜
Owner BEIHANG UNIV