Clock generator suitable for high-performance network processor chip

Abstract

The invention relates to a clock generator suitable for a high-performance network processor, which is a clock generator with selectable starting clock frequency hardware, adjustable operation software, low cost and simple and flexible design in a high-performance network processor chip and can provide fixed-frequency and variable-frequency clock frequencies. The clock generator comprises two parts, namely a frequency conversion clock generation module 101 and a fixed-frequency clock generation module 201. According to the clock generator, the frequency can be selected and matched in real time, frequency increasing and frequency decreasing in the chip operation process are supported, real-time parameter matching can be achieved through software, and meanwhile fixed network interface reference clock frequency can be provided. The fixed-frequency clock module and the variable-frequency clock module share an external BOOTMODE starting port, so that the hardware cost is reduced to the maximum extent while better compatibility of an external crystal oscillator low-frequency clock is ensured. The clock generator has the characteristics of simple principle, low hardware cost, flexibilityin clock generation and real-time selectable and configurable frequency, and can support full-chip clock generation of various high-performance network processor chips in the foremost network application.

Description

technical field [0001] The invention relates to a clock generator in a high-performance network processor chip oriented to network processing, in particular to a clock generator in a high-performance network processor chip with optional hardware for starting clock frequency, adjustable running software, and the ability to provide fixed-frequency and variable-frequency clocks frequency clock generator. Background technique [0002] The progress of network processing capability largely depends on the progress of hardware technology. The increasing complexity of current network processing applications, the continuous growth of throughput, and the continuous evolution of routing protocols have placed higher and higher performance requirements on network processing hardware. High-performance network processor chips often integrate complex processing logic and 10G and above high-speed For network interfaces, the chip design seeks a balance between higher-speed processing capabili...

AI Technical Summary

Problems solved by technology

[0005] The existing technology has the following disadvantages: the diversity of the needs for variable frequency and fixed frequency clocks in the chip increases the number of phase-locked loop PLLs generated by the basic clock, which leads to an increase in the number of DIP switches to start the BOOT mode, occupying too many chip pins ; Different application scenarios have different requirements on chip performance and power consumption. The logic processing unit in the chip may be adjusted to run at different clock frequencies during chip initialization or operation. However, the high-speed network interface of the network processor chip It must be fixed to run under a certain reference clock, and the diversity of requirements brings the complexity of the design

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