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Clock and data recovery circuit

A technology for recovering circuits and data, applied in the direction of electrical components, automatic power control, etc., can solve the problem of no state transition, unlocking, etc.

Pending Publication Date: 2019-10-11
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, for the application of a specific communication system, the transmission end may transmit a data signal that is 1 or 0 for a long time. In this case, the data signal may not change state for a long time, while the clock and data The frequency of the clock signal output by the recovery circuit will gradually unlock (Lose Lock)

Method used

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  • Clock and data recovery circuit

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Embodiment Construction

[0045] figure 1 It is a block diagram of a clock and data recovery (CDR) circuit 1 according to an embodiment of the present invention. The clock and data recovery circuit 1 includes a phase detector (Phase Detector) 10 a , an auxiliary module 12 , a charge pump (Charge Pump) 14 and a voltage controlled oscillator (Voltage Controlled Oscillator, VCO) 16 . The phase detector 10a receives a data signal DT and a first clock signal CK_CDR, and compares the phases of the data signal DT and the first clock signal CK_CDR to output a first output signal O1. The charge pump 14 is coupled to the phase detector 10a for outputting a control signal VCTL. The voltage controlled oscillator 16 is coupled to the charge pump 14 for generating a first clock signal CK_CDR according to the control signal VCTL. When the charge pump 14 receives the first output signal O1 and the first output signal O1 represents that the phase of the first clock signal CK_CDR lags behind the phase of the data sign...

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Abstract

A clock and data recovery circuit comprises a first phase detector, a first charge pump, a first voltage-controlled oscillator and an auxiliary module, and the auxiliary module comprises: an auxiliaryclock generator used for generating an auxiliary clock signal; a second phase detector which is coupled to the auxiliary clock generator and is used for comparing the auxiliary clock signal with thephase of a first clock signal output by the first voltage-controlled oscillator; and a multiplex selection unit which is used for outputting a multiplex output signal to the first charge pump according to a selection signal.

Description

technical field [0001] The present invention refers to a clock and data recovery circuit, especially a clock and data recovery circuit capable of preventing unlocking. Background technique [0002] Due to the rapid development of process technology, the operation speed of integrated circuits has been greatly improved. In a communication system with high-speed transmission, a clock and data recovery (CDR) circuit is often used to ensure that the transmitted input data can be read correctly. The clock and data recovery circuit needs to sample at the time corresponding to the rising edge or falling edge of the data signal transmitted by the transmission end (that is, the time when the data signal turns from 0 to 1 or from 1 to 0, or called the transition time), In order to perform correct phase and frequency tracking operations, the phase / frequency tracking capability of the clock and data recovery circuit depends on the stable and continuous occurrence of transition events of...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/089H03L7/099
CPCH03L7/0807H03L7/0891H03L7/099Y02D10/00
Inventor 王建中翁孟泽
Owner MEDIATEK INC