Metastable state detection and elimination circuit of synchronous clock ADC circuit
A technology for synchronizing clocks and eliminating circuits, applied in the field of ADC circuits, can solve problems such as inability to complete comparisons and long comparison times for comparators
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[0036] Below in conjunction with accompanying drawing and specific embodiment, the detection and elimination circuit of the metastable state of a kind of synchronous clock ADC circuit that the present invention proposes is described in further detail.
[0037] see Figure 8 , is a circuit diagram of the metastable detection and elimination circuit of the synchronous clock ADC circuit in a specific embodiment of the present invention.
[0038] In this specific embodiment, a metastable state detection and elimination circuit of a synchronous clock ADC circuit is provided, including: a metastable state flag signal generation circuit 1, which is used to connect to the comparator CMP of the synchronous clock ADC circuit The output terminal generates a metastable flag signal MD according to the output and reverse output of the comparator CMP to control the generation of a synchronous clock signal clkc, and the synchronous clock signal clkc is used to supply the comparator CMP and to...
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