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Metastable state detection and elimination circuit of synchronous clock ADC circuit

A technology for synchronizing clocks and eliminating circuits, applied in the field of ADC circuits, can solve problems such as inability to complete comparisons and long comparison times for comparators

Active Publication Date: 2019-11-01
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

like Figure 6b As shown, the comparison time of the current bit of the comparator will become very long, and eventually the comparison cannot be completed

Method used

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  • Metastable state detection and elimination circuit of synchronous clock ADC circuit
  • Metastable state detection and elimination circuit of synchronous clock ADC circuit
  • Metastable state detection and elimination circuit of synchronous clock ADC circuit

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Embodiment Construction

[0036] Below in conjunction with accompanying drawing and specific embodiment, the detection and elimination circuit of the metastable state of a kind of synchronous clock ADC circuit that the present invention proposes is described in further detail.

[0037] see Figure 8 , is a circuit diagram of the metastable detection and elimination circuit of the synchronous clock ADC circuit in a specific embodiment of the present invention.

[0038] In this specific embodiment, a metastable state detection and elimination circuit of a synchronous clock ADC circuit is provided, including: a metastable state flag signal generation circuit 1, which is used to connect to the comparator CMP of the synchronous clock ADC circuit The output terminal generates a metastable flag signal MD according to the output and reverse output of the comparator CMP to control the generation of a synchronous clock signal clkc, and the synchronous clock signal clkc is used to supply the comparator CMP and to...

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PUM

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Abstract

The invention relates to a metastable state detection and elimination circuit of a synchronous clock ADC circuit. The circuit comprises a metastable state flag signal generation circuit, wherein the control circuit is used for being connected to the output end of a comparator of the synchronous clock ADC circuit and generating a metastable state flag signal according to the output and reverse output of the comparator so as to control the generation of a synchronous clock signal, and the synchronous clock signal is used for being supplied to the comparator and providing a comparison clock for the comparator; a synchronous clock signal generation circuit, connected to the output end of the metastable state sign signal generation circuit, and used for generating a synchronous clock signal according to the metastable state flag signal, the synchronous clock signal generation circuit being further connected to the comparator and supplying the generated synchronous clock signal to the comparator, and when the comparator is in a metastable state, the synchronous clock signal is at a low level.

Description

technical field [0001] The invention relates to the field of ADC circuits, in particular to a metastable detection and elimination circuit of a synchronous clock ADC circuit. Background technique [0002] ADC (analog-to-digital Converter) is a circuit that converts analog signals into digital signals. As a bridge between analog signals and digital signals, ADCs are widely used in various circuits. For example: audio equipment, communications, satellites, precision instruments, etc. In recent years, with the development of technology, SAR ADC has attracted more and more attention due to its advantages of low power consumption. [0003] figure 1 It is a system block diagram of a common SARADC. It can be seen that SARADC mainly includes four parts: sampling circuit, DAC capacitor array, comparator, and logic circuit. For the detailed circuit of the logic circuit, see figure 2 , which mainly includes shift registers, data registers and output registers. [0004] The followi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/46
CPCH03M1/1009H03M1/46Y02D10/00
Inventor 张振伟董业民单毅
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI