A FPGA-based binary neural network acceleration method and system

Abstract

The invention discloses a binary neural network acceleration system based on FPGA, which utilizes a convolution kernel parameter acquisition module formed by FPGA, a binary convolution neural network structure and a cache module, the cache module is an on-chip memory of FPGA, and each module By obtaining the input feature map of the picture to be processed, obtaining the convolution calculation logic rules and corresponding binary convolution calculation, the FPGA traverses the convolution calculation of multiple threads according to the convolution calculation logic rules, and obtains the output features of the image to be processed Graph data, through this overall architecture, all the calculations of each layer in the binary neural network are offloaded to the on-chip memory, without relying on the interaction between off-chip memory and on-chip memory, thereby reducing the communication cost between memories and greatly improving Computational efficiency improves the detection speed of the image to be detected.

Description

technical field [0001] The invention belongs to the field of image processing, and in particular relates to an FPGA-based binary neural network acceleration method and system. Background technique [0002] Significant advances in artificial intelligence technology have begun to benefit all aspects of human life. From a vacuum robot in your home to an entire set of smart production equipment in a factory, many tasks in the world have already achieved a high degree of automation. Deep learning plays a pivotal role in this great technological revolution, and it has a wide range of applications in face recognition, object detection, image processing, and other fields. The main algorithm used is the convolutional neural network. This deep learning algorithm with better performance has been deployed in a large number of PCs, mobile phones and embedded dedicated accelerators to achieve various intelligent computing tasks. A better acceleration effect has been obtained. [0003] ...

AI Technical Summary

Problems solved by technology

[0004] However, all such mobile and embedded computing devices can only provide limited computing power and on-chip storage with a small capacity.

As the model structure of the convolutional neural network becomes more and more complex, the number of model layers becomes deeper, and the amount of model parameters increases, the deployment of convolutional neural networks on mobile and embedded terminals becomes more and more complex. difficulty

The huge amount of calculations all use 32bit floating-point numbers as operands to run on lightweight chips, which undoubtedly consumes a huge amount of computing resources, and it is also difficult to achieve better real-time results

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