Chip interconnection packaging method and interconnection packaging structure

Abstract

The invention provides a chip interconnection packaging method and an interconnection packaging structure, which are suitable for a flexible electronic packaging technology. The chip interconnection packaging method comprises steps: the chip is firstly packaged in a substrate by embedding, a hole is then punched in the substrate to obtain a through hole, and a pad of the chip is exposed; a multi-level step is then printed at the included angle between the hole wall of the through hole and the chip; and a wire is finally printed on the surface of the multi-level step, the wire is respectively connected with the circuit wiring of the substrate and the pad of the chip, and chip inter-layer interconnection is realized. According to the chip interconnection packaging method and the interconnection packaging structure provided in the invention, the multi-level step is then printed at the included angle between the hole wall of the through hole and the chip, wire printing in the through holebecomes simpler and more reliable, instable conductive performance of the wire caused by factors such as the gravity and a bonding force can be avoided, the inter-layer interconnection reliability isimproved, and the electrical connection reliability of the chip interconnection packaging structure is thus improved.

Description

technical field [0001] The invention relates to the technical field of electronic packaging, in particular to a method for interconnecting and packaging chips and an interconnecting and packaging structure. Background technique [0002] As the next generation of electronic revolution, flexible electronics are widely used in electronic communication, medical and military fields. In the existing flexible electronic packaging technology, the interconnection packaging structure of chips used for interlayer interconnection can be obtained by using traditional through-hole metallization technology and printing technologies such as 3D and inkjet. However, the packaging structure obtained through the traditional through-hole metallization process will easily cause problems such as metal peeling and fracture in the through-hole when the bending angle reaches a certain level; while the packaging structure obtained through 3D, inkjet and other printing technologies, such as figure 1 A...

AI Technical Summary

Problems solved by technology

However, the packaging structure obtained through the traditional through-hole metallization process will easily cause problems such as metal peeling and fracture in the through-hole when the bending angle reaches a certain level; while the packaging structure obtained through 3D, inkjet and other printing technologies, such as figure 1 As shown, the wires 30 are directly printed along the wall of the through hole 11 and respectively connected to the circuit wiring on the substrate 10 ( figure 1 not shown in ) and the pad 21 of the chip 20, this structure will cause the conductive performance of the wire 30 on the through hole 11 to be unstable due to factors such as gravity and bonding force of the wire 30 on the hole wall of the through hole 11 , and when it is greatly bent, a large amount of strain will be generated at the contact point between the chip 20 and the substrate 10, which will easily cause the wire 30 to break, peel off, etc.

[0003] Therefore, the existing traditional through-hole metallization process and 3D, inkjet and other printing technologies have the problem of low electrical connection reliability in the chip interconnection packaging structure.

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