I3C interface circuit compatible with SRAM bus

Abstract

The invention discloses an I3C interface circuit compatible with an SRAM bus. The I3C interface circuit comprises an operation layer circuit connected with an I3C communication controller, composed ofN configuration registers which are connected with the I3C communication controller and used for realizing a custom function, wherein each configuration register corresponds to a register interface and is used for communicating with the I3C communication controller; and a bus packaging layer circuit connected with the N configuration registers on the operation layer circuit, connected with an SRAM bus, and used for packaging register interfaces corresponding to the configuration registers into SRAM bus interfaces so as to realize communication with the SRAM bus. According to the I3C interfacecircuit, a register interface corresponding to a configuration register connected with an I3C communication controller can be packaged into an SRAM bus interface. The I3C communication controller isconnected with the SRAM bus, so that the connection with the SRAM bus is realized. The connection line of the I3C communication controller and a host system is simplified. A universal and flexible busconnection mode is provided, so that the I3C bus equipment has wider compatibility.

Description

technical field [0001] The invention relates to the technical field of integrated circuit IP core design, in particular to an I3C interface circuit compatible with an SRAM bus. Background technique [0002] The full name of IP core is intellectual property core (Intellectual Property Core), which refers to a chip design module provided by a certain party. Designers can use the IP core as the basis for logic design of ASIC or Field Programmable Logic Gate Array (FPGA) to shorten the design cycle and improve design quality and efficiency. [0003] With the rapid development of technologies such as 4G / 5G and the Internet of Things, sensors, as the entrance of data information collection and the "heart" of the Internet of Things, have received more and more attention. The I2C bus is widely used because of its simplicity, low resource consumption, multiple slaves, and low power consumption. However, with the development trend of smart and miniaturized sensors, the limitations of...

AI Technical Summary

Problems solved by technology

[0005] The invention provides an I3C interface circuit compatible with the SRAM bus to solve the problem that the connection between the communication controller and the host system is complicated and affects the efficiency of I3C communication

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