Three-dimensional memory device having deep isolation structure

Abstract

The method for forming a three-dimensional memory device includes: forming a peripheral circuit on a first side of a first substrate, the peripheral circuit including a first peripheral device and a second peripheral device, a first interconnect layer, and a shallow trench isolation (STI) structure between the first peripheral device and the second peripheral device; and forming a memory array including a plurality of memory cells and a second interconnection layer on the second substrate. The method includes bonding the first interconnect layer and the second interconnect layer and forming anisolation trench through the first substrate and exposing a portion of the STI structure. An isolation trench is formed through a second side of the first substrate opposite the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench, and performing a planarization process to remove a portion of the isolation material disposed on thesecond side of the first substrate.

Description

Technical field [0001] The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a method for reducing stress in a semiconductor wafer used to form a three-dimensional (3D) memory device. Background technique [0002] The planar memory cell is scaled to a smaller size by improving process technology, circuit design, programming algorithm and manufacturing process. However, when the feature size of the memory cell approaches the lower limit, the planar process and manufacturing technology become challenging and expensive. Therefore, the storage density for planar memory cells is close to the upper limit. Three-dimensional (3D) memory architecture can solve the density limitation in planar memory cells. Summary of the invention [0003] An embodiment of a three-dimensional (3D) capacitor structure for a memory device and a method for forming the three-dimensional capacitor structure are described in the present disclosure. [0004]...

AI Technical Summary

Problems solved by technology

However, planar processes and fabrication techniques become challenging and expensive when the feature size of memory cells approaches the lower limit

Therefore, the storage density for planar memory cells approaches the upper limit

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