High-precision dynamic comparator

Abstract

The invention discloses a high-precision dynamic comparator, and relates to the technical field of integrated circuits. The high-precision dynamic comparator comprises a latch circuit, a time sequencelogic circuit and at least two stages of dynamic pre-amplification circuits, the time sequence logic circuit and the at least two stages of dynamic pre-amplification circuits are connected with eachother, a first-stage dynamic pre-amplification circuit in the at least two stages of dynamic pre-amplification circuits receives the to-be-compared voltage, and amplifies the to-be-compared voltage according to a first clock signal sent by the time sequence logic circuit; the next stage of dynamic pre-amplification circuit in the at least two stages of dynamic pre-amplification circuits amplifiesan input signal according to a clock signal sent by the time sequence logic circuit, the input signal is a to-be-compared voltage preprocessed by the previous stage of dynamic pre-amplification circuit; and the latch circuit receives the output signal processed by the last stage of dynamic pre-amplification circuit, processes the output signal according to the latch clock signal sent by the time sequence logic circuit and outputs a comparison result. By adopting a cascade structure of multistage dynamic pre-amplification and latching, high comparison precision and no static power consumption are realized.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a high-precision dynamic comparator. Background technique [0002] In portable and Internet of Things application scenarios, low-power high-precision SAR ADC (Successive approximation register Analog-to-Digital Converter, successive approximation analog-to-digital converter) has become a hot research direction. As a comparator for the core circuit of SAR ADC, the Its power consumption and accuracy also put forward higher requirements. [0003] In the prior art, the dynamic comparator is fast and has no static power consumption, but its resolution is low, and it is generally used for SAR ADCs with medium and low resolutions; the precision of the static comparator is usually relatively high, but there are static Power consumption, typically used in high-resolution SAR ADCs. [0004] Such as figure 1 As shown, the dynamic comparator in the prior art generally adopts t...

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[0003] In the prior art, the dynamic comparator is fast and has no static power consumption, but its resolution is low, and it is generally used for SAR ADCs with medium and low resolutions; the precision of the static comparator is usually relatively high, but there are static power consumption, typically used in high-resolution SAR ADCs

[0004] like figure 1 As shown, the dynamic comparator in the prior art generally adopts the structure of a one-stage dynamic pre-amplification circuit pre_dcomp and a latch latch, but due to the limitation of noise and gain, it is generally only used for SARADC with a resolution below 12 bits, and it is difficult to achieve a higher resolution. high precision

like figure 2 As shown, the static comparator in the prior art is generally composed of two-stage static pre-amplification circuits pre_amp1, pre_amp2 and a latch latch. The static comparator is easy to achieve higher resolution, but the comparator has static power consumption, which is not suitable for low power application

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