Instruction processing method and storage controller
A memory controller and instruction processing technology, applied in register devices, program control design, electrical digital data processing, etc., can solve the problems of large bus delay and affecting processor throughput, etc.
Active Publication Date: 2022-01-11
SHENZHEN EPOSTAR ELECTRONICS LTD
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Problems solved by technology
However, since all elements of the memory controller 100 are attached to the system bus 120, this creates a considerable bus delay
This bus delay can seriously affect the throughput of the processor
Method used
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Embodiment Construction
[0038] figure 2 is a block diagram of a memory controller according to an embodiment of the present invention.
[0039] Please refer to figure 2 , the storage controller 200 according to an embodiment of the present invention includes a processor 210 and peripheral components 240(1)˜240(N). Processor 210 is coupled to peripheral components 240 ( 1 )˜ 240 (N) through system bus 220 . The processor 210 includes a processor core 211 and an instruction buffer 230 . The processor core 211 is coupled to the instruction buffer 230 through the local bus 260 . When the processor core 211 issues an instruction, the instruction will be sent to the instruction buffer 230 via the instruction path 201 . The instruction buffer 230 is, for example, a Static Random Access Memory (SRAM), a cache memory or other similar components. The peripheral components 240 ( 1 )- 240 (N) access instructions from the instruction buffer 230 and execute the instructions. Since the delay of the local bu...
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The invention provides an instruction processing method and a storage controller. The instruction processing method is applicable to the memory controller. The storage controller includes a processor and peripheral components. The instruction processing method includes: configuring the first instruction buffer and the second instruction buffer in the processor; configuring a synchronizer in the storage controller, and the synchronizer changes the value of the flag at a predetermined time interval to synchronize the first instruction buffer or the second instruction buffer The second instruction buffer is set to be valid; and when the first instruction buffer is valid and the processor issues an instruction, the processor temporarily stores the instruction in the first instruction buffer and one of the peripheral elements accesses the first instruction buffer Instructions in to perform corresponding operations. Therefore, the instruction processing method and storage controller of the present invention can effectively reduce bus delay and increase instruction execution speed.
Description
technical field [0001] The invention relates to an instruction processing method and a storage controller, in particular to an instruction processing method and a storage controller capable of increasing instruction execution speed. Background technique [0002] figure 1 is a known block diagram of a storage controller. exist figure 1 Among them, the memory controller 100 has a processor 110, a system bus 120, an instruction buffer 130, and peripheral elements 140(1)-140(N). When the processor 110 issues an instruction, the instruction will be transmitted from the instruction path 101 to the instruction buffer 130 and temporarily stored in the instruction buffer 130 . The peripheral components 140 ( 1 )˜140 (N) can access and execute instructions from the instruction buffer 130 through the system bus 120 . However, since all elements of the memory controller 100 are attached to the system bus 120, this creates a considerable bus delay. This bus delay can severely impact...
Claims
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IPC IPC(8): G06F9/30
CPCG06F9/30047G06F9/30098
Inventor 陈灿琳
Owner SHENZHEN EPOSTAR ELECTRONICS LTD