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A test method for low-voltage sram write half-select fault

A test method and fault test technology, applied in the direction of static memory, instrument, etc., can solve the problem of reducing test cost and achieve the effect of reducing test cost

Active Publication Date: 2020-10-02
NANJING UNIV OF POSTS & TELECOMM
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Problems solved by technology

This method can make up for the problem that the traditional algorithm cannot cover and write semi-selective faults, realize the coverage of the specified fault model, and effectively reduce the test cost

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  • A test method for low-voltage sram write half-select fault
  • A test method for low-voltage sram write half-select fault
  • A test method for low-voltage sram write half-select fault

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Embodiment Construction

[0035] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0036] The present invention aims at the problem that the semi-selection problem of 6T / 8T low-voltage SRAM is more and more serious due to the continuous serious process fluctuation under the advanced technology band, but the current traditional test algorithm cannot meet the problem of detecting the half-selection problem of writing, and proposes a targeted method A kind of test method of low-voltage SRAM writing half selection fault, such as figure 1 The steps shown include:

[0037] Step 1, write semi-selective fault model establishment.

[0038] The write half-selection problem refers to the half-selection phenomenon that occurs in other memory cells in the same row due to the effective word line during the write operation of a certain memory cell. Such as figure 2 As shown, when WL is turned on, the pull-down transistor and ...

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Abstract

A test method for low-voltage SRAM write half-selection faults, design test elements for write half-selection faults: {⇕W0⇕W1column0⇕R1column0⇕R0column0'⇕W0⇕W1column1⇕R1column1⇕R0column0'}, where {W1column0} and {W1column1 }Using the self-defined row read and write method, that is, an orderly read and write operation method for a specified range of row addresses, the data background is written into the storage unit with the same column address and the order of the row address is increased, and the sensitization is activated to cause a fault. Followed by a read operation, the read data is compared with the expected data, and if they are inconsistent, it is judged that a fault is detected. This method can make up for the problem that the traditional algorithm cannot cover and write semi-selective faults, realize the coverage of the specified fault model, and effectively reduce the test cost.

Description

technical field [0001] The invention belongs to the field of integrated circuit testing, and in particular relates to a testing method for low-voltage SRAM writing half-selection faults. Background technique [0002] The rapid development of artificial intelligence and the Internet of Things drives a new generation of automotive electronics, smart home, industrial manufacturing, etc. The demand for chips with high performance and low power consumption continues to grow, which also requires higher and higher requirements for memory. The area on the chip has reached more than 70%, and this ratio is still rising. Due to the demand for high performance and low power consumption, information must be stored near the CPU, that is, the memory needs to be embedded in the same chip position as the CPU, and the memory that can match the high performance and low power consumption of the CPU to the maximum can only It is SRAM, which has a fast read and write speed and is often used as a...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/54G11C29/52G11C29/14G11C29/44
CPCG11C29/14G11C29/44G11C29/52G11C29/54
Inventor 吕凯蔡志匡刘世欢王荧周正胡善文王子轩郭宇锋
Owner NANJING UNIV OF POSTS & TELECOMM