Tensor processor instruction set architecture

A processor and machine instruction technology, applied in the field of tensor processor instruction set architecture, can solve the problem of expensive machine learning

Active Publication Date: 2020-01-10
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Performing machine learning (such as but not limited to deep neural networks...

Method used

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  • Tensor processor instruction set architecture
  • Tensor processor instruction set architecture
  • Tensor processor instruction set architecture

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Embodiment Construction

[0020] Certain embodiments of the present technology involve hardware accelerators. Some embodiments relate to tensor register files in hardware accelerators. Some embodiments of the present technology relate to instruction set architectures in hardware accelerators.

[0021] Hardware accelerators can have various tensor operation calculators to perform various types of tensor operations. Tensor operations calculators may require tensors in order to operate on them. Efficient computations can be significantly slowed down if the tensor calculator has to wait for the required tensors to be provided.

[0022] In some embodiments, instead of having one large tensor register file storing tensors for all types of tensor operations, a hardware accelerator has multiple smaller tensor register files. These smaller tensor register files can be dedicated to one instance of the tensor calculator. Such a configuration can improve bandwidth by keeping the various tensor calculators busy...

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PUM

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Abstract

A hardware accelerator having an efficient instruction set is disclosed. An apparatus may comprise logic configured to access a first and a second machine instruction. The second machine instruction may be missing a tensor operand needed to execute the second machine instruction. The logic may be further configured to execute the first machine instruction, resulting in a tensor. The logic may be further configured to execute the second machine instruction using the resultant tensor as the missing tensor operand.

Description

Background technique [0001] Computing increasingly requires extremely powerful processors. For example, machine learning, such as but not limited to deep neural networks, requires processors capable of performing an extremely high number of operations per second. Performing machine learning, such as but not limited to deep neural networks, on a general-purpose central processing unit (CPU) can be prohibitively expensive. [0002] Hardware accelerators have been used to supplement processing performed on general-purpose CPUs. Contents of the invention [0003] Certain embodiments described herein relate to a hardware accelerator with an efficient instruction set. In one embodiment, an apparatus includes logic configured to access a first machine instruction and a second machine instruction in a set of machine instructions. The second machine instruction is missing a tensor operand required to execute the second machine instruction. The logic is also configured to execute ...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38G06N3/00
CPCG06F9/30036G06F9/30076G06F9/3012G06F9/30123G06F9/30163G06F9/3828G06F9/3836G06F9/3893G06N3/063G06F17/16G06F9/3016G06F9/30098
Inventor J·H·福沃斯K·奥恰洛夫S·K·莱因哈特E·S·钟刘明罡
Owner MICROSOFT TECH LICENSING LLC
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