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A method and system for receiving packets across CPUs in a multi-core system

A multi-core system, CPU core technology, applied in the field of home gateway devices, can solve the problems of IPI interrupts cannot be initiated, increase hardware costs, etc., and achieve the effects of improving cache hit rate, increasing affinity, and reducing latency

Active Publication Date: 2022-03-11
FENGHUO COMM SCI & TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the need to use a proprietary multi-channel DMA, this undoubtedly increases the hardware cost
Another method is to use IPI (Inter-Processor Interrupt, interrupt between processors) to allow other CPUs to process, but this IPI interrupt method also has the same problem as the above-mentioned business process, that is, when the packet receiving CPU is running at full load, even The IPI interrupt cannot be initiated, and this problem will also occur

Method used

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  • A method and system for receiving packets across CPUs in a multi-core system
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  • A method and system for receiving packets across CPUs in a multi-core system

Examples

Experimental program
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Embodiment 1

[0042] see figure 1 As shown, this embodiment provides a method for receiving packets across CPUs in a multi-core system, the method comprising the following steps:

[0043] A. According to the number of CPU cores in the multi-core system, allocate at least one packet receiving queue for each CPU; and allocate a timer. It can be understood that, at this time, the allocated timer is not working, and the allocated packet receiving queue is also empty.

[0044] B. Configure the message that needs to be received across CPUs and the designated CPU core for processing the message to the driver layer, start the timer and bind to the designated CPU core. It can be understood that the designated CPU core for processing the packet cannot be the core for receiving packets by DMA. That is to say, the designated CPU for processing packets received across CPUs is a CPU other than the core for receiving packets by DMA. This can effectively reduce the load on the core for receiving packets ...

Embodiment 2

[0055] see figure 2 As shown, this embodiment provides a method for receiving packets across CPUs in a multi-core system, the basic steps of which are the same as those in Embodiment 1, except that, as an optional implementation, step B of the method is specifically Including the following operations:

[0056] B1. When the business process needs to use the cross-CPU packet receiving function, configure the tuple information of the message that needs to be received across the CPU and the designated CPU core for processing the message, and configure the maximum tolerance of the business process for delay time; send the above configuration information to the driver layer;

[0057] B2, after the driver layer receives the configuration information, check whether the specified CPU core is the core of DMA receiving packets and the legality of other configuration parameters; if the specified CPU core is not the core of DMA receiving packets and other configuration parameters are val...

Embodiment 3

[0061] This embodiment provides a method for receiving packets across CPUs in a multi-core system, the basic steps of which are the same as in Embodiment 1, the difference is that, as a preferred implementation, after step D of the method, the following steps are also included: operate:

[0062] After the designated CPU core has processed a certain number of messages (for example, 100 messages have been processed), or when the queue is empty, the timer is restarted by the timeout interval of the previously set timer, and the operations of steps C and D are repeated.

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Abstract

The invention discloses a method and system for receiving packets across CPUs under a multi-core system, and relates to the technical field of home gateway equipment. The method includes: according to the number of CPU cores in the multi-core system, assigning at least one packet receiving queue for each CPU, and assigning a timer; configuring messages that need to receive packets across CPUs and a designated CPU core for processing the messages Go to the driver layer, start the timer and bind to the specified CPU core; when the DMA receives the message, the message that needs to be received across the CPU is attached to the packet receiving queue of the specified CPU core; when the timer expires After a period of time, the bound designated CPU core takes out the corresponding message from its corresponding packet receiving queue for processing. The present invention can not only effectively ensure that business messages (especially messages with high timeliness) are processed in time when the message flow that requires CPU to participate in processing is too large, but also has low hardware complexity and low use cost, which meets practical application requirements. need.

Description

technical field [0001] The invention relates to the technical field of home gateway equipment, and specifically relates to a method and system for receiving packets across CPUs in a multi-core system. Background technique [0002] In the home gateway equipment, with the development of technology, the bandwidth of the home is also increasing, from the previous ADSL (Asymmetric Digital Subscriber Line, asymmetric digital subscriber line) to the current XGPON (XG-Passive Optical Network, 10 Gigabit Gigabit passive optical network), the Internet speed has been significantly improved. [0003] With the development of broadband technology, more and more home users use WIFI to access the home gateway, which reduces a lot of wiring and makes the home environment more harmonious and beautiful. However, for home gateway devices, the price is constantly decreasing, but the demand is constantly increasing. As a result, in some scenarios, software must be used to complete some functions...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/54G06F9/48
CPCG06F9/546G06F9/4887
Inventor 谢绍新王中辉
Owner FENGHUO COMM SCI & TECH CO LTD
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