An all-digital sub-sampling phase-locked loop and its frequency range locking method

Abstract

The invention discloses an all-digital sub-sampling phase-locked loop and its frequency range locking method, comprising: a clock generation and control circuit; a sub-sampling phase detector, the first input end of which is connected to the first output end of the clock generation and control circuit ; The digital loop filter, the input end is connected with the output end of the sub-sampling phase detector; the digitally controlled oscillator, the first input end is connected with the output end of the digital loop filter, and the first output end is connected with the sub-sampling phase detector The second input terminal is connected; the auxiliary frequency locking circuit, the first input terminal is connected with the second output terminal of the clock generation and control circuit, the second input terminal is connected with the second output terminal of the numerically controlled oscillator, and the output terminal is connected with the digitally controlled oscillator connected to the second input. This invention solves the problems of small frequency locking range of the traditional sub-sampling phase-locked loop and high power consumption of the frequency-locking auxiliary circuit. The output mode of the sub-sampling phase detector is determined and switched by the all-digital mode switcher, and the frequency locking range is expanded.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an all-digital sub-sampling phase-locked loop and a frequency range locking method thereof. Background technique [0002] The all-digital phase-locked loop uses digital circuits to realize loop control, so it has a high degree of design and implementation flexibility, is easy to integrate with other on-chip systems, and can achieve better performance with the development of integrated circuit manufacturing processes, so it has a very wide range of applications. application. [0003] In the all-digital phase-locked loop, the sub-sampling loop structure is adopted. Under the control of the low-frequency reference clock, the high-frequency output of the oscillator is directly sampled to obtain phase error information, and then the output of the oscillator is adjusted through negative feedback control. Frequency, to achieve the function of the phase-locked loop. Since t...

AI Technical Summary

Problems solved by technology

This system and method aims to solve the problems of small frequency locking range of traditional sub-sampling phase-locked loops and large power consumption of frequency-locking auxiliary circuits. The working state of the sub-sampling phase detector is determined by an all-digital mode switcher, and the output mode is switched, so that The phase-locked loop can still work correctly when there is a large frequency error and the auxiliary frequency locking circuit is turned off, and the frequency locking range is expanded

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