Level conversion circuit

Abstract

The invention discloses a level conversion circuit which comprises a level shifting unit and a waveform shaping circuit. Signals of a first high-voltage output end and a second high-voltage output endof the level shifting unit pass through a second transmission gate of the waveform shaping circuit, a fifth phase inverter, a sixth phase inverter and a seventh phase inverter to be converted into gate signals of the fifth high-voltage NMOS transistor and the third high-voltage PMOS transistor which have the same phase, wherein the sum of duty ratios of the fifth high-voltage NMOS transistor andthe third high-voltage PMOS transistor is 100%. At the non-overlapping part of the gate signals of the two transistors, the fifth high-voltage NMOS transistor and the third high-voltage PMOS transistor are turned off or turned on at the same time, so that the duty ratio of the high-voltage output signal is approximately equal to half of the sum of the duty ratios of the gate signals of the two transistors. According to the level conversion circuit, the waveform shaping circuit B is used for restraining high-voltage output duty ratio imbalance caused by PVT conditions and working frequency changes, and the stable high-voltage output duty ratio is achieved under different PVT conditions and working frequencies.

Description

technical field [0001] The present invention relates to circuits, in particular to a level conversion circuit. Background technique [0002] Existing common level conversion circuits such as figure 1 As shown, it consists of 1 inverter, 2 low-voltage transistors and 4 high-voltage transistors. Inverter IN1 is used to generate a signal IN that is opposite to the phase of the low-voltage input signal INPUT; two high-voltage PMOS transistors MP1 and MP2 are used to pull up the high-voltage output signal OUTPUT level of the level conversion circuit, and two low-voltage NMOS transistors MN1, MN2 and two high-voltage NMOS transistors MN3 and MN4 are used to pull down the high-voltage output signal OUTPUT level of the level conversion circuit; the above-mentioned 6 transistors form a latch circuit. [0003] exist figure 1 In the level conversion circuit, when the low-voltage input signal INPUT is raised from low level to high level, the first low-voltage NMOS transistor MN1 and ...

AI Technical Summary

Problems solved by technology

The low-to-high and high-to-low transitions of the level shifting circuit have different delay times. As the operating frequency of the system increases, the difference in delay accounts for an increasing proportion of the signal period, which is affected by the integrated circuit. Influenced by the PVT (Process, Voltage and Temperature) conditions, the difference in current capability between the PMOS tube and the NMOS tube will cause a relatively obvious imbalance in the waveform and duty cycle of the output signal, which is very likely to cause the signal to fail to flip normally and the timing error

Moreover, due to the delay caused by the inverter IN1, it is no longer possible to consider the two signals input to the source of the low-voltage NMOS transistor as strictly inverting, which further expands the two mutually inverting outputs of the existing level conversion circuit. end( figure 1 Z and ZN) in the phase shift and waveform difference between the signals, the two low-voltage NMOS transistors MN1 and MN2 are also turned on at the same time, which aggravates the sensitivity of the output duty cycle to the operating frequency and hinders the improvement of the system speed

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