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Unsigned approximate multiplier with low logic complexity

An unsigned, multiplier technology, applied in the field of approximate computing, can solve the problems of complex logic design and energy consumption of multipliers, and achieve the effect of shortening the critical path, simple logic, and fewer logic gates

Pending Publication Date: 2020-02-21
NANJING UNIV
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Problems solved by technology

However, the multiplier has a complex logic design and is one of the most energy-consuming sub-operation units

Method used

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  • Unsigned approximate multiplier with low logic complexity
  • Unsigned approximate multiplier with low logic complexity
  • Unsigned approximate multiplier with low logic complexity

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Embodiment Construction

[0030] The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0031] An accurate multiplier operation is divided into the following three parts: generate partial products through logical AND gates; compress the partial product matrix using compressors (full adder and half adder); use adders to generate the final binary result. The approximate multiplier proposed by the present invention introduces an "approximation" in the compressed part of the partial product matrix. In the compression process, the approximate compressor in the scheme of the present invention is used to replace a part of half adders and full adders, so as to reduce the number of logic gates and reduce hardware overhead. At the same time, by applying the corresponding design in the present invention, the quantity and distribution of the exact compressor and the approximate compressor can be reasonably controlled to ensure higher accuracy.

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Abstract

The invention provides an unsigned approximate multiplier with low logic complexity. The approximate multiplier comprises a partial product matrix generation module, a first-stage approximate compression module, a second-stage approximate compression module, a second-stage accurate compression module and an adder module. Approximation is introduced into the compressed part of the partial product matrix, and an approximate compressor is completely used in the first stage of compression of the partial product matrix; in the second stage of partial product matrix compression, a full adder and a half adder are used in the high-order weight part, and only an approximate compressor is used in the low-order weight part. The approximate compressors used in the method only use logic AND gates and logic OR gates, and compared with accurate compressors (a half adder and a full adder), the logic is simple, and hardware expenditure is small. According to the approximate multiplier, the accuracy isguaranteed while the circuit performance is improved, and good balance is achieved in the aspects of precision and hardware cost.

Description

technical field [0001] The invention belongs to the field of approximate calculation, in particular to an unsigned approximate multiplier with low logic complexity and small area. Background technique [0002] In recent years, some applications with fault tolerance, such as multimedia signal processing, data mining, and deep learning, have received attention and been greatly developed. For practical applications, there is a demand for high computing performance with low energy consumption. However, such applications are usually computationally intensive and consume a large amount of energy. Developing such applications to embedded systems and mobile platforms is difficult, limited by power consumption and speed. But at the same time, this type of application has a certain degree of fault tolerance. Even if some errors and inaccuracies occur in the calculation process, the final correct and meaningful results can still be obtained. Therefore, combining the above two charac...

Claims

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Application Information

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IPC IPC(8): G06F7/523
CPCG06F7/523
Inventor 潘红兵王蔓蓁罗元勇安梦瑜
Owner NANJING UNIV
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