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Stress relaxed buffer layer on textured silicon surface

A stress relaxation and non-flat technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problem of reducing the quality of the top epitaxial layer

Pending Publication Date: 2020-02-28
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Dielectric residue will then degrade the quality of the top epitaxial layer

Method used

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  • Stress relaxed buffer layer on textured silicon surface
  • Stress relaxed buffer layer on textured silicon surface
  • Stress relaxed buffer layer on textured silicon surface

Examples

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Embodiment Construction

[0026] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. It is evident, however, that the example embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the illustrative embodiments. In addition, unless otherwise indicated, all numerical quantities, ratios, and numerical properties of constituents, reaction conditions, and the like used in the specification and claims should be understood to be understood by the term "about" All examples are modified.

[0027] The present disclosure solves the current problem of generating dislocation defects when growing semiconductor materials, such as stress relaxation buffer layers, on silicon wafers.

[0028] A method according to a disclosed embodim...

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Abstract

The invention relates to a stress relaxed buffer layer on a textured silicon surface. Specifically, a method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and a resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of theSi wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 201610511090.X, the filing date is June 30, 2016, and the title of the invention is "Stress relaxation buffer layer on non-flat silicon surface". technical field [0002] The present invention discloses the fabrication of semiconductor devices. In particular, the present invention discloses a Stress Relaxed Buffer (SRB) layer used in the fabrication of semiconductor devices in 14nm, 10nm, 7nm, 5nm and 3nm technology nodes. Background technique [0003] When silicon (Si, Silicon) wafers are used, the epitaxial growth of different semiconductor materials with different lattice constants and thermal expansion coefficients will cause defects, such as dislocation defects. This then leads to poor transistor performance and reliability issues. A substrate with a stress relaxation buffer layer, including stepped or graded GaAs (GaAs, Gallium Arsenide) or SiGe (Silicon Ger...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/306
CPCH01L21/02532H01L21/02546H01L21/30625H01L21/02381H01L21/0243H01L21/02433H01L21/0245H01L21/02461H01L21/02463H01L21/02543H01L21/0265H01L21/02538H01L21/02645H01L21/3212H01L29/0657H01L29/201H01L29/161
Inventor B·J·帕夫拉克
Owner GLOBALFOUNDRIES U S INC MALTA
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