Method and apparatus for inspecting stacked pairs of upper and lower wafers

Abstract

The invention provides a method for detecting the upper and lower layers of wafers, which includes scanning the set area on the surface of the first layer of graphic wafers, extracting the graphic profile data of the first layer of scanned pictures and comparing and saving them with the first layer layout data; the wafer continues to process Make the wafer have a second layer of graphics, scan the set area on the surface of the wafer with the second layer of graphics, extract the graphic profile data of the second layer of scanned pictures and compare them with the second layer of layout data and save the comparison Data; compare and save the first-level comparison data and the second-level comparison data in an overlay relationship. The device provided by the invention includes a storage module, a rasterization module, a matching module, a generation module, a calculation module, and a picture acquisition module. According to this, in the tape-out lithography process, without changing the process and without causing damage to the wafer, the obtained graphics of each layer are compared with the designed layout, and the layers are stacked and compared to detect the overlay accuracy and carry out Optical proximity correction.

Description

technical field [0001] The invention relates to the technical field of graphic test data collection such as optical proximity correction in process design of semiconductor device manufacturing, and in particular to a method for detecting upper and lower layers of wafers. [0002] The invention also relates to a device for implementing the method for detecting wafer stacked pairs. Background technique [0003] As the lithography feature size (Critical Dimension, CD) continues to decrease, the requirements for the overlay accuracy and critical dimension uniformity of the lithography machine are also increasing. The manufacture of integrated circuits usually includes dozens of photolithography processes. In order to ensure the corresponding relationship of each level, an overlay accuracy (overlay) that matches the size of the photolithographic features must be required. The difference between the exposure pattern and the actual position, that is, the pattern position offset, i...

AI Technical Summary

Problems solved by technology

[0011] Moreover, since the existing overlay technology can only be used to detect the overlay relationship between the graphic outline of the current layer and the layout data of the current layer, the overlay relationship between the graphic outlines on the wafer between different layers cannot be effectively realized.

Although the measurement can be realized by judging the overlapping relationship between different layers by slicing, this method is a destructive test. The test wafer cannot continue to be taped, and other wafers cannot be known. Due to the engineer's experience and the degree of manual fitting, the data may have certain fluctuation errors

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