Power semiconductor module substrate

Abstract

The invention discloses a power semiconductor module substrate. The power semiconductor module substrate includes a first power metal coating layer, a second power metal coating layer, a third power metal coating layer, a fourth power metal coating layer and auxiliary metal coating layers, wherein the auxiliary metal coating layers are formed between the first power metal coating layer and the second power metal coating layer and between the third power metal coating layer and the fourth power metal coating layer. A gate signal terminal is formed on the auxiliary metal coating layer, and the auxiliary metal coating layer extends in the arrangement direction of transistor chips and diode chips and at least extends to the position right opposite to the control electrode of the transistor chip located at the outermost edge in the arrangement direction. Thus, the stray inductance and the non-uniformity degree of the parallel chips can be reduced through reasonable driving loop arrangement.

Description

technical field [0001] The invention relates to a power semiconductor module substrate. Background technique [0002] In power semiconductor chips, transistor chips are usually used. For a transistor chip with a control terminal, the schematic diagram of the internal drive circuit of the power module is as follows: image 3 shown. Among them, Cg1, Cg2, and Cg3 respectively represent the gate capacitances of the three transistor chips connected in parallel, and the flow capacity of the chips is determined by the voltage on the gate capacitances. Tg and Te are ports for connecting the power semiconductor module to an external drive circuit for receiving drive signals. Rg0 and Lg0 are the stray resistance and stray inductance of the common part of the chip drive circuit respectively. Rg1, Lg1 and Rg2, Lg2 and Rg3, and Lg3 are the individual stray resistance and stray inductance caused by the position distribution of the three transistor chips respectively. During the turn-o...

AI Technical Summary

Problems solved by technology

[0004] If the stray parameters of the parallel chips are inconsistent, it will lead to inconsistent charging and discharging speeds of the gate capacitance during the switching process

As a result, the power current passing through the chip is uneven during the switching process, resulting in the inconsistency of the loss on the parallel chip, which is finally reflected in the temperature difference of the chip

When the power module is working at full power, the overtemperature and overcurrent caused by the uneven distribution of chip current may cause the failure of semiconductor components, affecting the reliability and output power of the module

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