Dynamic random access memory structure and method for preparing the same

Abstract

The present disclosure provides a dynamic random access memory structure and a method for preparing the same. The dynamic random access memory structure includes a substrate, a gate structure disposedin the substrate, a first source / drain region and a second source / drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the second source / drain region, a plurality of conductive pillars disposed on the landing pad, a conductive layer disposed over the plurality of conductive pillars, and a dielectric layer disposed between the conductive layer and the plurality of conductive pillars. The plurality of conductive pillars have at least a first width and a second width, and the first width and the second width are different from each other.

Description

technical field [0001] This application claims priority and benefits to U.S. Formal Application No. 16 / 117,668 filed on 2018 / 08 / 30, the contents of which are incorporated herein by reference in their entirety. [0002] The present invention relates to a dynamic random access memory (dynamic random access memory, DRAM) structure and a preparation method thereof, in particular to a dynamic random access memory memory unit (capacitor) structure and a preparation method thereof. Background technique [0003] The DRAM structure generally includes metal-oxide-semiconductor field effect transistor (MOSFET) elements and capacitors in or on a semiconductor substrate. These MOSFET elements and capacitors are connected in series with each other. In addition, memory cells of DRAM can be read and programmed using word lines and bit lines. [0004] The trend of increasing the storage density of integrated circuit memories to increase the amount of data stored on a single chip continues....

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Problems solved by technology

[0005] However, when the critical dimension of the cell structure of the DRAM is reduced to less than 20 nanometer (nm) level, the occupied area is too small to use the current photolithography manufacturing process to form a very high, Vertical Cylindrical Capacitors

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