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Method and system for wafer-level testing

A chip, integrated circuit technology, applied in the field of chip-level test and system

Pending Publication Date: 2020-03-17
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, current testing techniques can provide invalid reliability assessments due to unintended damage or degradation of integrated circuits during testing, so more effective stress methods for testing are necessary

Method used

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  • Method and system for wafer-level testing
  • Method and system for wafer-level testing
  • Method and system for wafer-level testing

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Embodiment Construction

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure of embodiments of the invention. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed on the first feature. Embodiments between a feature and a second feature such that the first feature and the second feature may not be in direct contact. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself dictate a ...

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Abstract

A method and system for wafer-level testing. The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an ICformed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.

Description

technical field [0001] Embodiments of the present invention relate to a wafer-level testing method and system. Background technique [0002] In semiconductor manufacturing, wafers typically undergo extensive processing to form integrated circuits. Various wafer level tests are performed to determine the performance and reliability of the integrated circuits under various conditions and wafer acceptance. Wafer level reliability testing is utilized to detect the potential for early failures associated with defects generated during the fabrication of integrated circuits. In general, reliability testing involves stressing the integrated circuits using various techniques such as on / off power cycling and applying voltages beyond normal operating conditions. However, current testing techniques can provide invalid reliability assessments due to unexpected damage or degradation of integrated circuits during testing, so more efficient stressing methods for testing are necessary. C...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26G01R31/28
CPCG01R31/2601G01R31/2642G01R31/2858G01R31/2879G01R31/2886
Inventor 军·何林裕庭林威勋郭永良卢胤龙
Owner TAIWAN SEMICON MFG CO LTD
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