49 results about "Power cycling" patented technology

Disclosed is a power metal-oxide-semiconductor field-effect transistor (MOSFET) diagnostic and lifetime estimation system and method, including the steps of: acquiring degradation data by conducting a degradation test; measuring potential failure precursors to provide early warning of failure; inspecting and diagnosing health condition of internal structure of the power MOSFET device using thermal transient measurement and scanning acoustic microscopy (SAM) images; repeating power cycling test and the measurements of potential failure precursors until the precursors reach a corresponding failure threshold; and estimating remaining lifetime of the power MOSFET device using an artificial intelligence (AI) algorithm.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

The invention provides an on-line power device aging test circuit facing vehicle working conditions, a comprehensive test analysis method and a comprehensive test analysis system. The aging test circuit comprises a tested three-phase six-bridge arm circuit composed of a tested power device, a temperature-sensitive electrical parameter measurement circuit, a bridge arm switching circuit and a standby bridge arm circuit. The temperature-sensitive electrical parameter measuring circuit is used for measuring the temperature-sensitive electrical parameter time-varying characteristic of the accessed tested power device; the bridge arm switching circuit is used for connecting the tested power device to the tested three-phase six-bridge arm circuit or the temperature-sensitive electrical parameter measuring circuit; the standby bridge arm circuit is used for replacing any bridge arm circuit where the tested power device connected to the temperature-sensitive electrical parameter measuring circuit is located so as to form a standby three-phase six-bridge arm circuit. The on-line power device aging test circuit provided by the invention can perform on-line detection on the aging condition of the vehicle inverter power device in a power cycle state.

A method for electronic device virtualization and management includes transmitting a signal to a server from a client. The signal is initiated by a user of a user interface of the client. The user interface of the client presents at least two devices to the user, which the user may interact with. The signal may include a power cycling instruction directed to at least one of the devices. When the server receives a communication back from the at least one device, it may send the information to the client, where the user interface may be updated in response to the communication. The devices may be controlled with other instructions, such as scheduling instructions, firmware update instructions, and configuration backup instructions. If a power device is virtualized, it may be controlled on a port-by-port basis.

The utility model discloses a power cycle batch comparison verification circuit for MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) devices, which relates to the technical field of power electronics and comprises a central control circuit, on-off control circuits, a current detection circuit and a display module, the central control circuit is electrically connected with the corresponding on-off control circuit through the current detection circuit, the central control circuit is electrically connected with the display module, and in the power cycle batch comparison verification circuit for the MOSFET device, the central control circuit controls the on-off of each on-off control circuit; the current detection circuit detects the current in the on-off control circuit and transmits the detected current to the central control circuit, the CPU in the central control circuit calculates the working power of the MOSFET according to the collected current and the conduction working voltage of the MOSFET, and related data is displayed through the display module. Therefore, the power cycle batch comparison detection of a plurality of MOSFET devices is realized.

A controller for a switched modulator receives an input voltage and generates a regulated output voltage. The controller activates a buck control circuit to generate a regulated output voltage having a first voltage value less than the input voltage. The controller activates a boost control circuit to return charge stored on an output capacitor at an output node to an input node to drive the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command indicating that the controller is to allow the output voltage to decay, the controller operates in a boost mode, using the boost control circuit to circulate the stored charge at the output node while reducing the output voltage.

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

The invention provides a power supply control method, device and equipment and a readable storage medium, and the method comprises the steps: receiving a power supply restart instruction issued by BMC equipment, the power supply restart instruction comprises a first delay time length and a second delay time length, and carrying out the analysis to obtain the first delay time and the second delay time; waiting for a first delay duration, and powering off the BMC equipment and powering off other components of the server; and waiting for a second delay duration, and re-electrifying the BMC equipment and electrifying other parts of the server. Through the technical scheme of the invention, the BMC issues the instruction with the double delay parameters to control the PSU to realize full power supply on-off, real AC restart can be completed without external equipment, the cost is reduced, and the test reliability and the automation degree are improved.

A method, computer system, and a computer program product are provided for operating a primary and a backup RAID storage array. A disk drive configuration is loaded into a disk controller in a primary RAID array and a disk controller in a backup RAID array. The disk drive configuration includes a schedule for a sequence of selectively power cycling the disk drives, which is executed by the disk controller in the primary and in the backup RAID arrays. Upon detecting a disk failure, each disk controller executes a recovery procedure according to instructions included in the disk drive configuration. Recovery procedure includes suspending power cycling all disk drives and powering on all intentionally powered off disk drives. Data is copied from the corresponding backup RAID array disk drive to primary RAID array to rebuild the failed drive. The RAID configuration remains in this state until failed disk drive is repaired.

The embodiment of the invention discloses a power cycle test circuit and method of a semiconductor device, electronic equipment and a medium, the power cycle test circuit comprises a plurality of parallel test branches, and each test branch comprises two tested devices which are reversely connected in series. Each tested device is composed of an insulated gate bipolar transistor with an anti-parallel diode, and the insulated gate bipolar transistor of one tested device and the anti-parallel diode of the other tested device form a current path. And the anti-parallel diode of one tested device and the insulated gate bipolar transistor of the other tested device form another current path. By adopting the embodiment of the invention, the thermal coupling effect of the anti-parallel diode and the IGBT device under the actual condition can be fitted, so that the temperature measurement result of the IGBT device is closer to the actual condition, and the service life evaluation of the power device is more accurate.

This application provides an online power device aging test circuit, a comprehensive test and analysis method, and a system for automotive applications. The aging test circuit includes a three-phase six-arm bridge circuit composed of the power devices under test, a temperature-sensitive electrical parameter measurement circuit, an arm switching circuit, and a spare arm circuit. The temperature-sensitive electrical parameter measurement circuit measures the time-varying characteristics of the temperature-sensitive electrical parameters of the connected power devices under test. The arm switching circuit connects the power devices under test to either the three-phase six-arm bridge circuit or the temperature-sensitive electrical parameter measurement circuit. The spare arm circuit replaces any arm circuit containing the power device connected to the temperature-sensitive electrical parameter measurement circuit, forming a spare three-phase six-arm bridge circuit. The online power device aging test circuit provided in this application can perform online detection of the aging status of automotive inverter power devices under power cycling conditions.

A method for predicting the remaining life of an IGBT module, which collects sensing data when the IGBT module performs power cycling under different working conditions, calculates transient thermal resistance data, and extracts and screens effective features therefrom; then uses source working condition data with remaining life labels and target working condition data whose remaining life is to be predicted as a training set to train a prediction model based on a probabilistic sparse self-attention mechanism; finally, in the online stage, the trained model is used to accurately predict the remaining life of the working condition. The present invention extracts and screens effective features from the transient thermal resistance data obtained from the power cycling of the IGBT module, uses a probabilistic sparse self-attention structure to further extract effective information, and measures the difference in deep features under different working conditions through the maximum mean discrepancy, so as to achieve cross-working condition prediction.

A method, computer system, and a computer program product are provided for operating a primary and a backup RAID storage array. A disk drive configuration is loaded into a disk controller in a primary RAID array and a disk controller in a backup RAID array. The disk drive configuration includes a schedule for a sequence of selectively power cycling the disk drives, which is executed by the disk controller in the primary and in the backup RAID arrays. Upon detecting a disk failure, each disk controller executes a recovery procedure according to instructions included in the disk drive configuration. Recovery procedure includes suspending power cycling all disk drives and powering on all intentionally powered off disk drives. Data is copied from the corresponding backup RAID array disk drive to primary RAID array to rebuild the failed drive. The RAID configuration remains in this state until failed disk drive is repaired.

The present invention discloses a power cycle test circuit and a test method for a power semiconductor device, including at least one test branch and a gate power supply module, and the structure of each test branch is the same; the output end of the heating current source is connected to the current bypass module, the positive output of the current bypass module is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the negative electrode of the current bypass module after passing through the semiconductor device under test; the gate power supply module is connected to the gate of the semiconductor device under test; the negative electrode of the test current source is connected to one end of the semiconductor device under test, and the positive electrode is connected to the positive electrode of the diode, and the negative electrode of the diode is connected to the other end of the semiconductor device under test. By adding a diode, the present invention can prevent current shunting, and can cooperate with the current bypass module to realize the switching of the heating current and the test current without adding switching devices, thereby avoiding the problem of insufficient switching speed caused by the turning on and off of the power device.

The invention discloses a power supply restart fault test method for an electric energy meter and the electric energy meter, and the method comprises the steps: cutting off the connection between the output end of a switching power supply input loop and the power supply end of a control circuit, enabling the output end of a battery to be connected with the power supply end of the control circuit, and enabling the electric energy meter to be in a preset radiation anti-interference test environment, obtaining a first power supply restart result; cutting off the connection between the output end of the battery and the power supply end of the control circuit, connecting the output end of the switching power supply input loop with the power supply end of the control circuit, and connecting the electric energy meter to the power supply end of the control circuit to obtain a second power supply restart result; and then the two power restart results are combined to judge the power restart positioning point of the power restart fault, so that the power restart fault positioning problem of the electric energy meter is solved.

This invention provides a power cycle testing method and apparatus for power semiconductor devices, relating to the field of semiconductor device testing technology. It is applied to a test circuit containing multiple power units. The method includes: applying a periodic switching drive signal to the test circuit, causing the switching transistors within the test circuit to operate in a dynamic switching mode simulating actual operating conditions, thereby applying cyclic electrothermal stress to the power semiconductor device under test (DUT) contained in the test circuit; for the same test circuit, changing the drive signal to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the DUT; and measuring the on-state voltage drop of the DUT when a stable current flows through it in the static conduction mode.

A fault reset system for an appliance is provided. The fault reset system includes a controller comprising a sensing circuit, the sensing circuit configured to determine one or more sensor values associated with one or more capacitive touch sensors of the appliance. The fault reset system further includes a reset circuit configured to reset the sensing circuit based on a reset signal provided by the controller. The reset circuit is configured to reset the sensing circuit by power cycling the controller.

Provided are a power electronic device degradation monitoring apparatus and method. The apparatus includes a power cycling test system, a heat sink, an acoustic emission sensor, a power electronic device under test, and a signal processing system. The acoustic emission sensor is configured to collect a stress wave signal released by the power electronic device under test at each turn-off time and transmitted by the heat sink. The signal processing system is configured to preprocess the stress wave signal collected by the acoustic emission sensor, extract feature components from a preprocessed stress wave signal, calculate key feature parameters of each feature component, and compare the calculated key feature parameters with key feature parameters of the power electronic device under test in a healthy status to obtain a degradation status of the power electronic device under test.

The present invention relates to a method of controlling gears in a vehicle. The method comprising: receiving, by an electrical control unit, ECU, associated with an autonomy stack of the vehicle, a gear selection control signal sent by a gear selection module, GSM, to the gears of the vehicle to select a gear from a plurality of gears; modifying, by the ECU, the gear selection control signal based on a target trajectory of the vehicle generated by the autonomy stack; sending, by the ECU, the modified gear selection control signal to the gears through a controller area network, CAN; then, sending, by the ECU, a power cycling signal to the GSM to turn a power of the GSM off then subsequently turn the power of the GSM back on, after a pre-determining power cycling time.

A method for electronic device virtualization and management includes transmitting a signal to a server from a client. The signal is initiated by a user of a user interface of the client. The user interface of the client presents at least two devices to the user, which the user may interact with. The signal may include a power cycling instruction directed to at least one of the devices. When the server receives a communication back from the at least one device, it may send the infomlation to the client, where the user interface may be updated in response to the communication. The devices may be controlled with other instructions, such as scheduling instructions, firmware update instructions, and configuration backup instructions. If a power device is virtualized, it may be controlled on a port-by-port basis.

A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.

A storage device may maintain persistent data after converting from firmware associated with a first mode to firmware associated with a second mode. The device receives a firmware package associated with the second mode, determines when the package includes a descriptor, and executes a copy macro in the descriptor to translate a first data structure used in the first mode to the second data structure used in the second mode. When the device receives a commit command and determines that the second data structure is in a volatile memory, the device copies the second data structure to a non-volatile memory. After completing the commit command and power cycling, when the device is being formatted in the second mode, the device reads the second data structure from the non-volatile memory, transfers the second data structure to a persistence module, and formats in the second mode.

A voltage across a first capacitor and a voltage across a second capacitor are set to a reference voltage via a reference voltage source. The first and second capacitors are disconnected from the reference voltage source and the reference voltage is turned-off. A processing device turns-on the reference voltage in response to determining a voltage difference between the first and second capacitors due to leakage current is at or above a threshold level. The first and second capacitors are connected to the reference voltage source to return the voltage across the first capacitor and the voltage across the second capacitor to the reference voltage.

To provide a mordant layer which is a new mordanting layer between adjacent conductive polymer layers and reduces peeling or breakage of a conductive polymer cathode.SOLUTION: In the electrolytic capacitor 10, a mordant layer 20 is provided on a primary conductive polymer layer 18 provided on a dielectric 16, the mordant layer is composed of a crosslinking agent and a predetermined mordant compound, a secondary conductive polymer layer 22 is provided on the mordant layer, and the mordant layer is crosslinked to the primary conductive polymer layer 18 and the secondary conductive polymer layer 22.SELECTED DRAWING: Figure 1

The application discloses a bus discharge control method for power quick restart, which comprises a bus discharge control circuit and operation steps. The bus discharge control circuit comprises a key switch S connected with a power supply, a bus circuit connected with one end of the key switch S, an input enable circuit connected with one end of the switch S, and a semiconductor switch circuit connected with the key switch S and the bus circuit and used for starting a sleep state of a control system. A signal of the input enable circuit is provided by a system MCU. The application has the advantages of simple structure, key switch control power restart, system sleep, no power consumption, input key switch for wake-up, simple application, power supply with an enable function, controllable input on-off of the bus and the power supply, and solution to the problem of quick start caused by integrated bus discharge.

A voltage across a first capacitor and a voltage across a second capacitor are set to a reference voltage via a reference voltage source. The first and second capacitors are disconnected from the reference voltage source and the reference voltage is turned-off. A processing device turns-on the reference voltage in response to determining a voltage difference between the first and second capacitors due to leakage current is at or above a threshold level. The first and second capacitors are connected to the reference voltage source to return the voltage across the first capacitor and the voltage across the second capacitor to the reference voltage.

The invention relates to a power supply module capable of automatically restarting during single-particle latch-up and a power supply restarting method. The power supply module comprises a direct-current voltage source V1, a switch SW1, a switch SW2 and a voltage converter U1, wherein the direct-current voltage source V1 is used for outputting direct-current voltage, and the direct-current voltage serves as input voltage of the voltage converter U1; the switch SW1 and the switch SW2 are used for controlling connection or disconnection between the direct-current voltage source V1 and the voltage converter U1 through switch switching, and when single-particle latch occurs, automatic restart of the voltage converter U1 is achieved through on-off circuit switching. The voltage converter U1 is used for converting and outputting the input direct-current voltage into the voltage required by a rear-end chip or module, and meanwhile, the output voltage of the voltage converter U1 is also used as an enable signal to control the on or off of the switch SW1 and the switch SW2. The power supply module can be automatically restarted when single-particle latch occurs, and long-term reliable operation of a spacecraft electronic system in an extreme environment is ensured.

The system and method according to the present disclosure determines the duration of the current command queue in the controller, executes all complete commands that can be executed before the low power cycle begins. When the device enters power mode, the unexecuted commands can be fetched. In an alternative embodiment, a portion of the commands that can be executed before the low power cycle begins are executed, where the unexecuted portion of the commands are stored on the device, in an Always On (AON) memory. When the device enters power mode, the unexecuted portion is fetched and executed.

A method, computer system, and a computer program product are provided for operating a primary and a backup RAID storage array. A disk drive configuration is loaded into a disk controller in a primary RAID array and a disk controller in a backup RAID array. The disk drive configuration includes a schedule for a sequence of selectively power cycling the disk drives, which is executed by the disk controller in the primary and in the backup RAID arrays. Upon detecting a disk failure, each disk controller executes a recovery procedure according to instructions included in the disk drive configuration. Recovery procedure includes suspending power cycling all disk drives and powering on all intentionally powered off disk drives. Data is copied from the corresponding backup RAID array disk drive to primary RAID array to rebuild the failed drive. The RAID configuration remains in this state until failed disk drive is repaired.

A storage device, and a method for operating a storage device. In some embodiments, the storage device includes storage media, and the method includes: determining, by the storage device, that the storage device is in a first fault state from which recovery is possible by power cycling the storage device or by formatting the storage media; determining, by the storage device, that the storage device is in a second fault state from which partial recovery is possible by operating the storage device with reduced performance, with reduced capacity, or in a read-only mode; and operating the storage device with reduced performance, with reduced capacity, or in the read-only mode.