16 results about "Power cycling" patented technology

The utility model discloses a power cycle batch comparison verification circuit for MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) devices, which relates to the technical field of power electronics and comprises a central control circuit, on-off control circuits, a current detection circuit and a display module, the central control circuit is electrically connected with the corresponding on-off control circuit through the current detection circuit, the central control circuit is electrically connected with the display module, and in the power cycle batch comparison verification circuit for the MOSFET device, the central control circuit controls the on-off of each on-off control circuit; the current detection circuit detects the current in the on-off control circuit and transmits the detected current to the central control circuit, the CPU in the central control circuit calculates the working power of the MOSFET according to the collected current and the conduction working voltage of the MOSFET, and related data is displayed through the display module. Therefore, the power cycle batch comparison detection of a plurality of MOSFET devices is realized.

A controller for a switched modulator receives an input voltage and generates a regulated output voltage. The controller activates a buck control circuit to generate a regulated output voltage having a first voltage value less than the input voltage. The controller activates a boost control circuit to return charge stored on an output capacitor at an output node to an input node to drive the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command indicating that the controller is to allow the output voltage to decay, the controller operates in a boost mode, using the boost control circuit to circulate the stored charge at the output node while reducing the output voltage.

A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.

This application provides an online power device aging test circuit, a comprehensive test and analysis method, and a system for automotive applications. The aging test circuit includes a three-phase six-arm bridge circuit composed of the power devices under test, a temperature-sensitive electrical parameter measurement circuit, an arm switching circuit, and a spare arm circuit. The temperature-sensitive electrical parameter measurement circuit measures the time-varying characteristics of the temperature-sensitive electrical parameters of the connected power devices under test. The arm switching circuit connects the power devices under test to either the three-phase six-arm bridge circuit or the temperature-sensitive electrical parameter measurement circuit. The spare arm circuit replaces any arm circuit containing the power device connected to the temperature-sensitive electrical parameter measurement circuit, forming a spare three-phase six-arm bridge circuit. The online power device aging test circuit provided in this application can perform online detection of the aging status of automotive inverter power devices under power cycling conditions.

The invention discloses a power supply restart fault test method for an electric energy meter and the electric energy meter, and the method comprises the steps: cutting off the connection between the output end of a switching power supply input loop and the power supply end of a control circuit, enabling the output end of a battery to be connected with the power supply end of the control circuit, and enabling the electric energy meter to be in a preset radiation anti-interference test environment, obtaining a first power supply restart result; cutting off the connection between the output end of the battery and the power supply end of the control circuit, connecting the output end of the switching power supply input loop with the power supply end of the control circuit, and connecting the electric energy meter to the power supply end of the control circuit to obtain a second power supply restart result; and then the two power restart results are combined to judge the power restart positioning point of the power restart fault, so that the power restart fault positioning problem of the electric energy meter is solved.

This invention provides a power cycle testing method and apparatus for power semiconductor devices, relating to the field of semiconductor device testing technology. It is applied to a test circuit containing multiple power units. The method includes: applying a periodic switching drive signal to the test circuit, causing the switching transistors within the test circuit to operate in a dynamic switching mode simulating actual operating conditions, thereby applying cyclic electrothermal stress to the power semiconductor device under test (DUT) contained in the test circuit; for the same test circuit, changing the drive signal to a measurement drive signal to switch the test circuit to a static conduction mode, thereby forming a DC current path for measuring the on-state voltage drop of the DUT; and measuring the on-state voltage drop of the DUT when a stable current flows through it in the static conduction mode.

To provide a mordant layer which is a new mordanting layer between adjacent conductive polymer layers and reduces peeling or breakage of a conductive polymer cathode.SOLUTION: In the electrolytic capacitor 10, a mordant layer 20 is provided on a primary conductive polymer layer 18 provided on a dielectric 16, the mordant layer is composed of a crosslinking agent and a predetermined mordant compound, a secondary conductive polymer layer 22 is provided on the mordant layer, and the mordant layer is crosslinked to the primary conductive polymer layer 18 and the secondary conductive polymer layer 22.SELECTED DRAWING: Figure 1

The application discloses a bus discharge control method for power quick restart, which comprises a bus discharge control circuit and operation steps. The bus discharge control circuit comprises a key switch S connected with a power supply, a bus circuit connected with one end of the key switch S, an input enable circuit connected with one end of the switch S, and a semiconductor switch circuit connected with the key switch S and the bus circuit and used for starting a sleep state of a control system. A signal of the input enable circuit is provided by a system MCU. The application has the advantages of simple structure, key switch control power restart, system sleep, no power consumption, input key switch for wake-up, simple application, power supply with an enable function, controllable input on-off of the bus and the power supply, and solution to the problem of quick start caused by integrated bus discharge.

A voltage across a first capacitor and a voltage across a second capacitor are set to a reference voltage via a reference voltage source. The first and second capacitors are disconnected from the reference voltage source and the reference voltage is turned-off. A processing device turns-on the reference voltage in response to determining a voltage difference between the first and second capacitors due to leakage current is at or above a threshold level. The first and second capacitors are connected to the reference voltage source to return the voltage across the first capacitor and the voltage across the second capacitor to the reference voltage.

The invention discloses a physical power-off synchronous restart circuit, and the circuit comprises a power-off detection circuit which is connected with a power supply circuit and a control circuit, and is used for receiving a high-low level change signal so as to detect whether the control circuit is powered off or not; the power supply restart circuit is connected with the power supply circuit and used for controlling the power supply circuit to be powered off and restarted; the power failure restart trigger circuit is respectively connected with the power supply circuit, the power failure detection circuit and the power supply restart circuit and is used for triggering the power supply restart circuit to work when the power failure detection circuit detects power failure; the power-on activation circuit is respectively connected with the power supply circuit and the power-off restart trigger circuit and is used for activating the power-off restart trigger circuit during power-on, the power-off restart trigger circuit drives the power supply restart circuit to control the power supply circuit to be powered off after power-off of the controller is detected, and power supply is restarted after a period of time; therefore, the control circuit and the external equipment can synchronously supply power to work.

Approaches presented herein provide for the management of power supplied to server trays, such as allowing for power cycling of individual server trays in a server rack powered by a DC busbar. In at least one embodiment, a timer circuit may be triggered by a power cycling command to prevent power from a power source, such as a busbar, to be provided to processing circuitry within a server tray of a server rack, except the timer circuit. The power can be caused be no longer available to the processing circuitry, ending operation of logical operations of the processing circuitry. After a period of time, the timer circuit can generate a signal to cause the power from the power source to be made available to the processing circuitry, allowing for resumed operation. At least a minimum amount of capacitance may be discharged from the processing circuitry during the period of time.

This invention relates to the field of vehicles, and more particularly to a power battery pre-charge control circuit, a vehicle, and a power battery pre-charge control method. This invention controls the electronic fan to reverse to output a high-voltage pre-charge signal, so that the bus capacitor can be pre-charged based on the high-voltage pre-charge signal. When the voltage across the bus capacitor is close to the total voltage of the power battery system, the relay contacts are closed, thus avoiding the problem in the prior art where repeated power cycling in vehicles can damage the pre-charge circuit and affect vehicle operation.

A charging and discharging device is disclosed, aiming to charge and supply power simultaneously while reducing power cycling stress. As a charging and discharging ECU installed in an electric vehicle, used to control the charging and supply of power to an external power source, the charging and discharging ECU includes: a receiving unit that receives a charging and supply start time sent from a collector that manages the external power source; a prediction unit that predicts the charging and supply start time sent from the collector; and a setting unit that determines the charging start time and charging end time for timed charging. The setting unit determines the charging end time based on the charging and supply start time predicted by the prediction unit.

An integrated router is provided. The integrated router includes at least one network interface, a power supply input, a power supply output, and a power cycling switch. The at least one network interface is operative to place a first network device in electronical communication with a second network device. The power supply input is operative to receive electrical power from a power supply. The power supply output is operative to provide the electrical power to the second network device. The power cycling switch electrically connects the power supply input to the power supply output and is operative to be toggled by a remote network device via the at least one network interface so as to power cycle the second network device.

This invention provides a power semiconductor package structure with electrothermal topology separation and its formation method. The package structure includes: a power semiconductor chip having an active device region and a peripheral non-active region; a first terminal and a second terminal located on one side of the first surface of the chip; a vertical conductive structure located in the peripheral non-active region and connected to the first terminal; a back conductive layer connected to the vertical conductive structure and the active device region; and a thermally conductive insulating layer and a bottom heat diffusion layer located on the back side of the back conductive layer. The first terminal, the vertical conductive structure, the back conductive layer, the active device region, and the second terminal are sequentially electrically connected to form a conductive path. The thermally conductive insulating layer and the bottom heat diffusion layer do not carry the main current and are electrically isolated from the conductive path. By establishing physical separation between the main current path and the heat flow path in the package architecture, the current loop area is reduced to decrease parasitic inductance, the heat dissipation area is increased, and the thermal resistance is reduced, thereby improving reliability and service life under high-power cycling.

A memory sub-system comprises a power management component comprising a plurality of regulators configured to output respective operating voltages for the memory sub-system. The power management component comprises a power management integrated circuit (PMIC) and is configured to monitor voltage levels of the plurality of regulators and prevent an event of the memory sub-system from occurring until the monitored voltage levels of a set of the plurality of regulators are determined to have reached respective threshold voltage levels.