Chaos-based initial vector generation algorithm and IP core thereof

A technology of initial vector and generation algorithm, applied in secure communication through chaotic signals, countermeasures to attack encryption mechanisms, digital transmission systems, etc., can solve the problems of difficult application of the system, easy information loss, etc. Effect

Active Publication Date: 2020-04-10
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, in wireless communication, the information in the channel is easily lost. When an encrypted communication system can only perform correct decryption when the information is received completely, this system is difficult to apply.

Method used

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  • Chaos-based initial vector generation algorithm and IP core thereof
  • Chaos-based initial vector generation algorithm and IP core thereof
  • Chaos-based initial vector generation algorithm and IP core thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] A chaotic initial vector generation algorithm, the initial vector generation method is as follows:

[0037] Step 1. First, input a 32-bit initial value x into the sequence generator based on Logistic chaos 0 , the 128-bit initial key KEY of the ZUC encryption algorithm is divided into 16 32-bit key[i] (0≤i≤15), so that key[i] (0≤i≤15) are respectively used as the Logistic chaotic iterative mapping enter,

[0038] Among them, the expression of Logistic chaotic iterative mapping is as follows:

[0039] x n+1 =4x n (1-x n ) (1)

[0040] where x 0 is the initial value, n is the number of iterations, and x n Consists of 32-bit registers;

[0041] Step 2. Assign key[0] to 32-bit x 0 , and calculate x 1 =4x 0 (1-x 0 );

[0042] Step 3. Assign key[i] to key[i-1], and then assign x 1 Assigned to key[15], for all x generated in order 1 Intercept the 128-bit sequence at the end of the sequence at intervals of 1024 bits as an initial vector, and turn back to step 2. ...

Embodiment 2

[0050] FPGA of IP Core Based on Chaotic Initial Vector Generation Algorithm

[0051] Such as figure 2 As shown, the initial vector generation module has 6 input and output signals, and its signal definitions are listed in Table 1.

[0052] Table 1 Top-level module signal list

[0053]

[0054]

[0055] In addition to the clock signal and reset signal, the initial vector generation module also has a control signal "start". The main workflow of the initial vector generation module is explained here: when the initial vector generation module is powered on, it first performs a reset operation, and then The initial vector generation module enters the standby state. When the start signal is valid for the first time, the initial vector generation module will download the key and run for 1024 clock cycles, and then output an initial vector. At the same time, the initial vector valid flag signal "IV output is valid" pulls One beat higher means that the signal on the output sig...

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Abstract

The invention provides a chaos-based initial vector generation algorithm and an IP core thereof, and the generation algorithm comprises the steps: inputting a 32-bit initial value x0 into a Logistic chaos-based sequence generator, and dividing a 128-bit initial key KEY of a ZUC encryption algorithm into 16 32-bit keys [i]; assigning the key [0] to 32 bits x0, and calculating x1 = 4 * 0 (1-x0); assigning the key [i] to the key [i-1], then assigning the x1 to the key [15], and intercepting a 128-bit sequence at the end of all x1 sequences generated in sequence every 1024 bits as an initial vector; the IP core for generating the algorithm comprises an initial vector generation module generated by the method, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module. According to the method, the good randomness of the chaotic pseudo-random sequence is utilized, so that the unpredictability of the initial vector isgreatly improved.

Description

Technical field: [0001] The invention relates to the field of data encryption, in particular to a chaotic initial vector generation algorithm and its IP core. Background technique: [0002] Zu Chongzhi (referred to as ZUC) sequence cipher is a synchronous sequence cipher algorithm. The algorithm input includes two parts, namely the initial key (Initial Key, KEY for short) with a bit width of 128 bits and the initial vector (Initial Key) with a bit width of 128 bits. Vector, referred to as IV). The ZUC sequence cipher algorithm uses the input 128-bit KEY and 128-bit initial vector to generate a key stream to encrypt digital information. [0003] The ZUC sequence cipher algorithm is the third set of international encryption algorithms recommended by the International Organization for Standardization 3GPP (3rd Generation Partnership Project). According to the ZUC sequence encryption algorithm promulgated by 3GPP, the initial vector is generated in a fixed way and structure by...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/00H04L9/22
CPCH04L9/001H04L9/002H04L9/0662H04L2209/12
Inventor 丁群冯凯王传福李孝友余龙飞唐薪玥
Owner HEILONGJIANG UNIV
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