DDR signal time sequence calibration method and device

Abstract

The invention discloses a DDR signal time sequence calibration method and a device, and the method is executed by a control module, and comprises the steps: obtaining a current to-be-calibrated signalcombination transmitted between the control module and a DDR chip; determining a current compensation time difference corresponding to the current to-be-calibrated signal combination according to a preset compensation time difference library; wherein the compensation time difference library comprises N compensation time differences, the N compensation time differences are in one-to-one correspondence with the N groups of to-be-calibrated signal combinations, and the compensation time differences are obtained in advance according to actual transmission time differences and specified transmission time differences corresponding to the to-be-calibrated signal combinations; wherein the specified transmission time difference corresponding to each to-be-calibrated signal combination is determined according to a DDR protocol, and N is greater than 1; and according to the current compensation time difference, performing time sequence calibration on the current to-be-calibrated signal combination. Through internal timing sequence calibration, signals transmitted between the control module and the DDR chip can meet the transmission timing sequence requirement of a DDR protocol, miniaturization design of the circuit board is facilitated, and the wiring difficulty of the circuit board is reduced.

Description

technical field [0001] The invention relates to the technical field of DDR, in particular to a DDR signal timing calibration method and device. Background technique [0002] Since a double data rate synchronous dynamic random access memory chip (Double Data Rate, DDR) has a double data transmission rate, DDR chips are more and more widely used. The DDR protocol specifies the transmission timing requirements for different signals to ensure that the DDR chip can process the corresponding signals, such as the transmission timing requirements between different DQ signals, the transmission timing requirements between DQ signals and DQS signals, The transmission timing requirements between the DQ signal and the CLK signal, the transmission timing requirements between the addressing signal and the CLK signal, etc. [0003] In order to ensure that the transmission timing of different signals meets the relevant regulations of the DDR protocol, the existing technology often designs t...

AI Technical Summary

Problems solved by technology

[0004] However, the solutions in the prior art often require the transmission line to be wound in a serpentine manner to achieve the required line length, such as figure 1 As shown, this will affect the miniaturization design of the circuit board and increase the difficulty of wiring the circuit board

Images