Array substrate and display panel

Abstract

The present invention provides an array substrate and a display panel. The display panel includes an array substrate, and the array substrate includes a thin film transistor area, a main pixel area and a sub pixel area; the main pixel area and the sub pixel area are arranged on the same side of the thin film transistor area, and the sub pixel area is arranged in a U-shape half surrounding the main pixel area . The invention reduces the area occupied by the thin film transistor area, and at the same time, the sub-pixel area forms a semi-enclosed structure around the main pixel area, which can increase the distance between the main pixel area and the main data wiring, reduce the coupling capacitance between them, and improve the color partial. Further, removing the common electrode wiring between the two adjacent sub-pixel regions and the source-drain wiring surrounding the main pixel region and the sub-pixel region can shorten the distance between the second pixel electrode boundaries of the adjacent two sub-pixel regions. Therefore, the distribution width of the pixel electrodes in the main pixel area and the sub-pixel area is increased, and the aperture ratio is increased.

Description

technical field [0001] The present invention relates to the field of display technology, and in particular, to an array substrate and a display panel. Background technique [0002] Multi-domain alignment liquid crystal displays (MVALCDs) have been widely used in large-size liquid crystal displays and TV applications due to their advantages of high contrast and wide viewing angle. [0003] With the evolution of the screen size to a larger screen, the 8-domain pixel design is valued in large-size displays due to its excellent viewing angle performance. [0004] like figure 1 As shown, it is a schematic plan view of an existing array substrate with an 8-domain pixel structure. The array substrate 90 includes a thin film transistor area 901, a main pixel area 902 and a sub pixel area 903 located on the upper and lower sides of the thin film transistor area. The thin film transistor area 901 mainly Using a 3T or 3T plus structure, the main pixel region 902 and the sub-pixel reg...

AI Technical Summary

Problems solved by technology

[0007] Since a large number of common electrode lines 94 and source-drain lines 92 surrounding the main pixel area 902 and sub-pixel area 903 are arranged inside the array substrate 90, and the distance between the common electrode lines 94 and the pixel electrodes 91 is relatively long, the source-drain line The pole line 92 has a width of 3um and is relatively wide, and needs to be spaced apart from the data line 93, resulting in a distance of 21.5um between two adjacent sub-pixel regions 903, so a large amount of aperture ratio will be sacrificed, resulting in wear and tear. drop in transmittance

Images