Optimization method for software and hardware division and scheduling of dynamic partially reconfigurable system-on-chip

Abstract

The invention provides an optimization method for software and hardware division and scheduling of a dynamic partially reconfigurable system-on-chip. Firstly, modeling is performed on an application and a system, and a software and hardware partitioning problem is classified into a hybrid linear programming model; the model is solved by utilizing an operational research solving tool, and an application deployment scheme is output, wherein the application deployment scheme comprises task execution starting time, task execution ending time, task reconstruction time mapped to a reconstruction area and mapping from the task to a processor. Compared with an existing software and hardware partitioning algorithm, the MILP avoids the risk that a random optimization algorithm is prone to falling into local optimum, and the solving result of the algorithm is more appropriate to actual application.

Description

technical field [0001] The invention relates to the problem of partitioning and scheduling of software and hardware of a dynamic partially reconfigurable system-on-chip, in particular to the problem of partitioning and scheduling of software and hardware executed on a heterogeneous system integrated with a Field Programmable Gate Array (FPGA) and a microprocessor. Background technique [0002] FPGA is a programmable logic gate array with powerful parallel computing capabilities. The dynamic partially reconfigurable system-on-chip integrates a CPU and a field programmable gate array (FPGA) with dynamic partially reconfigurable characteristics. Dynamic partial reconfiguration means that the system can dynamically change the function of a certain area at runtime without interrupting the running tasks in other areas. It can realize the parallel execution of tasks and realize the spatial multiplexing of resources; at the same time, the same area can execute different application...

AI Technical Summary

Problems solved by technology

However, although the ASIC special chip has high computing power, it has defects such as poor flexibility, long development cycle and high cost.

The GPU that has been favored in recent years also has bottlenecks such as high power consumption

Traditional hardware programming also has the dilemma of long development cycle and large resource usage

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