Method and device for reducing first-layer convolution calculation delay of CNN accelerator

Abstract

The invention relates to the field of hardware accelerated convolutional neural networks, and aims to improve the calculation parallelism of first-layer convolution by optimizing the calculation modeof the first-layer convolution, thereby effectively reducing the calculation delay of the first-layer convolution. Therefore, the technical scheme adopted by the invention is as follows: the method and the device for reducing the calculation delay of the first-layer convolution of the CNN accelerator are characterized in that when the first-layer convolution is calculated, parallel calculation iscarried out from different channel directions, and meanwhile, parallel calculation is also carried out on different feature image blocks in the same channel; for other convolution layers, parallel computing is carried out only from different channel directions. The method and device are mainly applied to integrated circuit design and manufacturing occasions.

Description

technical field [0001] The invention relates to the field of hardware accelerated convolutional neural networks, in particular to the field of parallel design of convolutional neural network accelerators. Specifically, the invention relates to a method and a device for reducing the first-layer convolution calculation delay of a convolutional neural network accelerator. Background technique [0002] In recent years, Convolutional Neural Network (CNN) has been widely used in computer vision tasks such as image classification, object detection and scene segmentation due to its high classification accuracy. [1] . However, the commonly used CNN model has a huge amount of calculation, and it will be a very time-consuming task to implement the convolutional neural network algorithm with software. Therefore, the design method of hardware accelerated CNN algorithm has emerged. The hardware accelerator maps the neural network algorithm to the hardware and makes full use of the para...

AI Technical Summary

Problems solved by technology

Since the single calculation engine uses the same circuit to meet the calculation requirements of all convolutional layers, compared with the fully customized architecture, it effectively saves hardware resources and improves the versatility of the circuit, but its disadvantages are also obvious: since all convolutional layers Using the same calculation mode, when individual convolutional layers (especially the first layer convolution) operate according to this mode, due to the failure to maximize the use of parallel computing resources, the calculation efficiency is low and the delay is large

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