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Defect monitoring method

A defect monitoring and chip technology, used in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as decreasing and increasing the yield of wafers, and achieve the effect of improving the yield of finished products

Active Publication Date: 2020-04-21
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, the existing defect scanning machine captures the defect by comparing the chip (Die) with the left and right chips of the chip. Therefore, scanning at least three chips in each row can make the scanning go on normally, and less than two The rows of chips cannot be scanned using existing technologies, thus increasing the risk of Wafer Low Yield

Method used

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Embodiment 1

[0035] Reference figure 2 , Embodiment 1 of the present invention provides a defect monitoring method, including:

[0036] S11: Perform graphic scanning on the product, and retrieve wafers with rows that do not satisfy three chips;

[0037] S12: Count the total number of chips on the wafer and number each chip;

[0038] S13: Compare each chip with the previous one;

[0039] S14: Obtain the final comparison data.

[0040] Specifically, first, the number of chips is counted according to the mask pattern used on the wafer, and the distribution of the chips is understood in real time. E.g figure 1 , This chip has rows with less than three chips, so this chip is screened out. After that, the number of chips is scanned by existing technology.

[0041] In this embodiment, the wafer is divided into multiple chips, and the chips are in the form of multiple rows and multiple columns, and are arranged on the wafer in the form of an array. Wafers are generally round, with multiple chips in the s...

Embodiment 2

[0044] Reference image 3 , The second embodiment of the present invention provides a defect monitoring method, including:

[0045] S21: Perform graphic scanning on the product, and retrieve wafers with rows that do not satisfy three chips;

[0046] S22: Divide all chips on the wafer into two areas, the first area contains the chips on the periphery of the wafer, and the second area contains the internal chips;

[0047] S23: sequentially compare each chip in the first area with the previous adjacent chip one by one;

[0048] S24: Compare the chip in the second area with the two chips before and after to obtain comparison data of the chips in the two areas.

[0049] In this embodiment, the method for dividing the first area and the second area is as follows: any chip in any row or column is the outermost chip, and the row or column in which it is located is classified as the first One area, the remaining chips are classified as a second area. The wafer is round, and the shape composed ...

Embodiment 3

[0052] Reference Figure 4 , The third embodiment of the present invention provides a defect monitoring method, which is characterized in that it includes:

[0053] S31: Perform graphic scanning on the product, and retrieve chips that do not satisfy the three-chip rows;

[0054] S32: Divide the wafer into multiple grid areas, compare the chip in each grid with the chip preceding the chip in the same grid, to obtain comparison data of multiple grids.

[0055] In this embodiment, the grid division method refers to the pattern mask to divide the entire wafer into multiple grid regions. Since the wafer is a prototype and the grid area is square, after division, the number of chips in a grid in the edge area of ​​the wafer is not consistent with the number of chips in the middle grid.

[0056] In this embodiment, each grid contains one or more chips. The division of the grid can directly use the mask to divide the wafer into multiple grids, the size of the grid is variable, for example F...

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Abstract

The invention provides a defect monitoring method which comprises the following steps: performing graphic scanning on a product, and retrieving a wafer with rows which do not meet three chips; dividing all the chips on the wafer into two regions, the first region including the chips on the periphery of the wafer, and the second region including the chips inside; sequentially comparing each chip inthe first region with the previous adjacent chip one by one; and comparing the chips in the second region with the front chip and the rear chip of the second region respectively to obtain the comparison data of the chips in the two regions. According to the defect monitoring method, any defect monitoring method can be used for detecting the chips of which the number of the chips in a row is lessthan three, namely, all the chips on the wafer can be scanned and detected so that the yield of wafer finished products is improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a defect monitoring method. Background technique [0002] Facing the increasingly mature semiconductor industry, improving product yield has become a major element of core competitiveness. How to effectively capture defects in real time through the defect scanning machine in each step of the production line's yield inspection, so as to control the deficiencies in the process and prevent greater profit loss, has become very important. [0003] At present, the existing defect scanning machine captures defects by comparing the chip (Die) with the left and right chips of the chip. Therefore, there are at least three chips in each line to make the scan go on normally, but less than two The line of chips cannot be scanned using existing technology, which increases the risk of wafer low yield (Wafer Low Yield). Summary of the invention [0004] The purpose of the present invent...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/12H01L22/20
Inventor 傅佳意
Owner SHANGHAI HUALI MICROELECTRONICS CORP