High-speed low-power-consumption majority arbitration circuit for clock data reset circuit

Abstract

The invention discloses a high-speed low-power-consumption majority arbitration circuit for a clock data reset circuit in the technical field of integrated circuit design, and the circuit comprises aphase discrimination part and a voting part; the phase discrimination part comprises a first phase discriminator and a second phase discriminator; the voting part comprises a first voting circuit anda second voting circuit; the first phase discriminator and the second phase discriminator are used for inputting four data at the same time and sending a detection phase result to the first voting circuit. According to the invention, on the premise that the same phase detection and voting functions are achieved, the extremely high speed and low power consumption are kept. The invention creativelyprovides the high-speed low-power-consumption voting circuit to eliminate invalid output of phase non-operation, so the power consumption of the system is greatly reduced; the overall circuit structure is simplified, the speed of most arbitration circuits is increased, the overall performance of the clock data reset circuit is improved, and the requirements of the Internet of Things for high speedand low power consumption of electronic products are met.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a high-speed, low-power majority arbitration circuit for a clock data reset circuit. Background technique [0002] The traditional majority arbitration circuit structure such as figure 1 , the circuit includes four phase detectors, three arbitration circuits, the output of the first and second phase detectors to the first arbitration circuit, the output of the third and fourth phase detectors to the second arbitration circuit, the first and second The output of the second arbitration circuit is sent to the third arbitration circuit. The first, second, and third arbitration circuits use a plurality of two-to-one selectors. For a high-speed clock data reset circuit, it is difficult to achieve high-speed requirements if a traditional majority arbitration circuit structure is used. In addition, multiple alternative selectors will invisibly bring greater power cons...

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a high-speed low-power majority arbitration circuit for clock data reset circuit, to solve the existing traditional majority arbitration circuit structure proposed in the above background technology is difficult to achieve high-speed requirements and multiple secondary selection An invisible selector will bring greater power consumption problems

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