A fpga single event inversion verification circuit and method

Abstract

The invention discloses an FPGA single particle inversion verification circuit and method. In this technical solution, the FPGA is integrated with a programming and error correction control module, an error correction encoder, a check code storage module, a configuration storage module, and an error correction decoder. The programming and error correction control module reads from the outside of the FPGA FPGA configuration file, the error correction encoder generates a check code according to the FPGA configuration file, the check code storage module writes the check code, and the error correction decoder uses the check code written by the check code storage module and the configuration storage module to write The imported FPGA configuration file is used for single event inversion verification. The check code is generated inside the FPGA, and the FPGA configuration file does not contain additional check codes, so there is no need to process the extra check codes, the FPGA configuration file becomes smaller, shortens the FPGA configuration time, improves the FPGA configuration efficiency, and satisfies the requirements of the system. Real-time requirements.

Description

technical field [0001] The present invention relates to the technical field of FPGA, and in particular, to an FPGA single particle inversion verification circuit and method. Background technique [0002] Field-Programmable Gate Array (FPGA) is widely used in various fields, such as industrial control, embedded system, cryptography, aerospace, network and so on. FPGA has the characteristics of high performance and low one-time engineering cost, which is suitable for the realization of large circuits and the rapid development of new products. With the exponential growth of system performance and capacity, the noise margin of integrated circuits decreases, the power supply voltage decreases, and the possibility of low-energy particles-induced Single Event Upset (SEU) increases, making the FPGA configuration inside the FPGA. Files are susceptible to soft errors by SEU. Single event inversion is also known as single event flip. [0003] For the SEU problem, the prior art discl...

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Problems solved by technology

Since the FPGA configuration file contains additional ECC check codes, the FPGA needs to process the extra ECC check codes in the FPGA configuration file first. The FPGA configuration file is large, which increases the FPGA configuration time and reduces the FPGA configuration efficiency; especially in the FPGA In application scenarios with large design scale and complex FPGA configuration files, the efficiency of FPGA configuration in the prior art drops significantly

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