DDR SDRAM physical layer interface circuit and DDR SDRAM control device

Abstract

The invention provides a DDR SDRAM physical layer interface circuit and a DDR SDRAM control device. Disclosed is a DDR SDRAM physical layer interface circuit that uses less circuit area and can adjustthe phase of the signal between a memory controller and a storage circuit, the DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the referenceclock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock;a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.

Description

technical field [0001] The present invention relates to a double data rate synchronous dynamic random access memory (DDR SDRAM) physical layer interface circuit and a DDR SDRAM control device, in particular to a DDR SDRAM physical layer interface circuit with smaller circuit area and / or less power consumption with DDR SDRAM control device. Background technique [0002] With the evolution of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) technology, the applicant proposed in US Patent No. 9,570,130B2 to use a delay-locked loop (delay-locked loop, DLL) to handle high-speed DDR SDRAM applications. Timing is not easy to converge and the clock tree latency is too long. However, the applicant believes that there is room for further improvement in terms of the circuit area and energy saving of the above-mentioned prior art. Contents of the invention [0003] An object of the present invention is to provide a double data rate synchronous dynamic random acc...

AI Technical Summary

Problems solved by technology

[0002] With the evolution of Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) technology, the applicant proposed in US Patent No. 9,570,130B2 to use a delay-locked loop (delay-locked loop, DLL) to handle high-speed DDR SDRAM applications. Timing is not easy to converge and the clock tree latency is too long

Images