Write operation auxiliary circuit

Abstract

A write operation auxiliary circuit comprises a pre-charging circuit, a driving signal circuit, a programmable time delay circuit, a charge pump, a write driving circuit and a column selector, the pre-charging circuit and a pre-charging signal output end are coupled with a pre-charging signal input end of the driving signal circuit, and two voltage output ends are coupled with a first bit line anda second bit line respectively; two input ends of the driving signal circuit are respectively coupled with the first bit line and the second bit line, and two output ends of the driving signal circuit are respectively coupled with two input ends of the programmable time delay circuit; the output end of the programmable time delay circuit is coupled with the first end of the charge pump; the second end of the charge pump is coupled with the ground end of the write driving circuit; two input ends of the write driving circuit are respectively used for inputting a first level and a second level with opposite phases, and two output ends of the write driving circuit are coupled with two input ends of the column selector; and two output ends of the column selector are respectively coupled with the first bit line and the second bit line. The write operation auxiliary circuit does not need to depend on external input of driving signals of corresponding time sequences.

Description

technical field [0001] The invention relates to the technical field of SRAM, in particular to a write operation auxiliary circuit. Background technique [0002] With the development of advanced technology, changes in process parameters brought about by the process, such as random doping fluctuations and other effects, make the design of SRAM more and more challenging. Among them, the stability of write operation is a major difficulty in SRAM design. In order to improve the anti-noise capability during the write operation, an existing solution is to increase the write assist circuit to pull the bit line of the SRAM down to a negative voltage, which in turn increases the speed of the write operation and increases the stability of the write operation. [0003] In the prior art, the write operation auxiliary circuit pulls down the voltage of the bit line through the charge pump, and the driving signal of the charge pump is usually driven by an external driving signal with a corr...

AI Technical Summary

Problems solved by technology

[0003] In the prior art, the write operation auxiliary circuit pulls down the voltage of the bit line through the charge pump, and the driving signal of the charge pump is usually driven by an external corresponding timing driving signal, and the timing requirements are relatively strict.

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