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A clamping circuit that can be used for both electrostatic discharge and surge protection

A surge protection and clamping circuit technology, applied in the direction of emergency protection circuit devices, emergency protection circuit devices, circuit devices for limiting overcurrent/overvoltage, etc. Surge protection and other issues to achieve the effect of low turn-on voltage

Active Publication Date: 2022-02-22
芯峰科技(广州)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a clamping circuit that can be used for electrostatic discharge and surge protection at the same time, which solves the problem that the prior art cannot achieve low turn-on voltage and cannot be used for ESD and surge protection at the same time

Method used

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  • A clamping circuit that can be used for both electrostatic discharge and surge protection
  • A clamping circuit that can be used for both electrostatic discharge and surge protection
  • A clamping circuit that can be used for both electrostatic discharge and surge protection

Examples

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Embodiment Construction

[0036] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0037] refer to figure 1 , is an existing RC-triggered clamping circuit, and its structure is formed by cascading RC network, inverter and clamping transistor, wherein the RC network is formed by series connection of resistor R01 and capacitor C01; the inverter is composed of PMOS The transistor Mp01 and the NMOS transistor Mn01 are connected in series; the clamping transistor adopts the NMOS transistor Mn02.

[0038] refer to figure 2 , is an existing diode-triggered clamping circuit, and its structure is formed by cascading a voltage detector, an inverter and a clamping transistor, wherein the voltage detector is formed by connecting a resistor R00 and a diode string DS0 in series; the inverter It is composed of PMOS transistor Mp0 and resistor R03 connected in series; the clamping transistor adopts NMOS transistor Mn03.

[0039] It can...

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PUM

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Abstract

A clamping circuit of the present invention that can be used for electrostatic discharge and surge protection at the same time consists of three RC networks, three inverters, a voltage divider, a comparator, a pull-down path, two pull-up paths and a clamp Transistors are cascaded; first RC network, first inverter, second RC network, voltage divider, comparator, third RC network, second inverter, third inverter, first pull-up path, the second pull-up path and the front end of the clamping transistor are all connected to the VDD wire; the first RC network, the first inverter, the second RC network, the voltage divider, the comparator, the third RC network, the second inverter The terminals of the phase device, the third inverter, the pull-down path and the clamping transistor are all connected to the GND terminal; the ends of the first pull-up path and the second pull-up path are connected to the front end of the pull-down path. The clamping circuit of the invention meets the requirements of simultaneous electrostatic discharge and surge protection.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit protection, is a voltage-sensitive clamping circuit structure, and relates to a clamping circuit which can be used for electrostatic discharge and surge protection at the same time. Background technique [0002] Electrostatic discharge (ESD) is an important reliability issue for integrated circuits. ESD refers to that after the charged body accumulates charge, it contacts the integrated circuit and generates charge transfer, forming a discharge process and causing damage to the integrated circuit. Surge is another common discharge phenomenon that integrated circuits face. Usually, the surge current flows into the power line of the integrated circuit and causes damage to the circuit. It is a typical electrical overstress (EOS) event. In general, the ESD current rise time is short (less than 10ns), and the total discharge time is also short (less than 1us); the surge current rise time is...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02H9/04H02H9/02
CPCH02H9/04H02H9/02
Inventor 杨兆年张超刘俊杰
Owner 芯峰科技(广州)有限公司