3D NAND memory and manufacturing method thereof

Abstract

The invention provides a 3D NAND memory and a manufacturing method thereof. The method comprises the steps of forming a stacked structure on a substrate, wherein the stacked structure comprises a storage block which is divided by a plurality of second grid line gaps continuously extending in the first direction, channel structures which are distributed in an array mode are formed in a through holearea of the storage block, first grid line gaps which extend in the first direction and are distributed at intervals are further formed in the through hole area of the storage block, and the first grid line gaps can be through holes formed in the middle of the channel structures of the through hole area. The first grid line gap is beneficial to the growth of an epitaxial structure near the innerrow channel structure in the through hole area, so that no gap exists near the inner row channel structure, and the risks of electric leakage and the like in the later period of the device are avoided. Besides, a sacrificial layer in the stacked structure is removed through the first grid line gap and the second grid line gap, so that the time required for removing the sacrificial layer can be remarkably reduced, the formation of a grid conductive material is facilitated at the same time, and the production cost can be correspondingly reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit are increasingly favored. [0003] In the 3D NAND process, gate line gaps are usually formed to form stacked gate layers. In order to control the effective gate area, the size of the gate line gaps needs to be limited, thus making the size of the gate line gaps very limited. When the common source is subsequently formed through the gate line gap and the contact part of the common source is further formed, the position of the contact part and the common source is slightly deviated, which will cause the contact part to bridge the gate layers on both sides of the common source...

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND process, gate line gaps are usually formed to form stacked gate layers. In order to control the effective gate area, the size of the gate line gaps needs to be limited, thus making the size of the gate line gaps very limited. When the common source is subsequently formed through the gate line gap and the contact part of the common source is further formed, the position of the contact part and the common source is slightly deviated, which will cause the contact part to bridge the gate layers on both sides of the common source, resulting in leakage and other hazards, seriously affecting the use of the device

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