Cache hit state-based processor chip false security dependency conflict identification method

A cache hit and processor technology, applied in electrical digital data processing, computer security devices, instruments, etc., can solve problems such as static analysis is difficult to ensure coverage, dynamic analysis consumes a lot of time, performance degradation and other problems, to ensure performance and safety The balance between performance and performance, and the effect of ensuring safety

CN111241551AActive Publication Date: 2020-06-05INST OF INFORMATION ENG CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Publication Date
2020-06-05

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Abstract

The invention provides a cache hit state-based processor chip false security dependency conflict identification method, and belongs to the field of processor microarchitecture design. On the premise that it is guaranteed that speculative execution vulnerability based on a cache side channel is defended, the performance loss caused by introducing safety characteristics into a speculation executionmechanism is reduced; according to the method, reasons of cache state changes in attacks are distinguished, the locality of a cache structure is utilized, only small changes need to be made on the cache, an operating system or software system information is not needed, the method is transparent to software, and meanwhile an attacker cannot utilize the software to intervene in judgment of pseudo-security dependencies.
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Description

technical field

[0001] The invention belongs to the field of processor micro-architecture design, and relates to a method for designing a safe processor micro-architecture based on a cache hit state for identifying false security dependency conflicts. Background technique

[0002] Speculative execution is one of the basic performance optimization measures to improve instruction parallelism in high-performance processors. However, the disclosure of the "Specter" class vulnerability reveals that there are security risks in the speculative execution technology in the existing high-performance processors. In different application scenarios from mobile to cloud, almost all commercial high-performance processors face the risk of being attacked by attackers to steal sensitive information within a wrongly speculated window period.

[0003] The generation of "ghost" vulnerabilities depends on two points. 1) The processor uses speculative execution to reduce the performance loss cau...

Examples

Embodiment Construction

[0014] In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

[0015] The method for identifying false security dependency conflicts of a processor chip based on a cache hit state proposed by the present invention mainly includes the following technical solutions:

[0016] 1) Dynamically judge false security dependencies

[0017] When accessing the cache unit, according to the security dependency flag of the current memory access operation request, and according to whether the current memory access operation hits the tag (Tag) in the cache at this level, that is, whether the content of the current memory access operation request has been recorded in the Tag array, To judge whether the security dependency of the current memory access operation is true or false:

[0018] If the current memory access operation misses in th...