Recognition method of processor chip false security dependency conflict based on cache hit status

A cache hit and processor technology, applied in electrical digital data processing, computer security devices, instruments, etc., can solve problems such as static analysis is difficult to ensure coverage, performance degradation, dynamic analysis consumes a lot of time, etc., to ensure performance and safety The balance between performance and performance, and the effect of ensuring safety

Active Publication Date: 2022-01-25
INST OF INFORMATION ENG CHINESE ACAD OF SCI
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Problems solved by technology

However, static analysis is difficult to guarantee coverage, and dynamic analysis consumes a lot of time
In order to further describe the connection between the speculative execution side channel and the speculative execution instruction, the security dependency establishes a dependency relationship between the trigger speculative execution operation and the speculative execution instruction ahead, but simply blocks the memory access operation that is marked as suspicious according to the dependency analysis. will cause severe performance degradation

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  • Recognition method of processor chip false security dependency conflict based on cache hit status

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Embodiment Construction

[0014] In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

[0015] The method for identifying false security dependency conflicts of a processor chip based on a cache hit state proposed by the present invention mainly includes the following technical solutions:

[0016] 1) Dynamically judge false security dependencies

[0017] When accessing the cache unit, according to the security dependency tag of the current memory access operation request, and according to whether the current memory access operation hits the tag (Tag) in the cache at this level, that is, whether the content of the current memory access operation request has been recorded in the Tag array, To judge whether the security dependency of the current memory access operation is true or false:

[0018] If the current memory access operation misses in the...

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Abstract

The invention provides a method for identifying false security dependency conflicts of a processor chip based on a cache hit state, which belongs to the field of processor microarchitecture design, in order to reduce the speculative execution mechanism under the premise of ensuring defense against speculative execution loopholes based on cache side channels The performance loss caused by the introduction of security features in this method, by distinguishing the reasons for the change of the cache state in the attack, using the locality of the cache structure, only a small change in the cache is required, and no information about the operating system or software system is required. The software is transparent, and at the same time, attackers cannot use the software to interfere with the judgment of such false security dependencies.

Description

technical field [0001] The invention belongs to the field of processor micro-architecture design, and relates to a method for designing a safe processor micro-architecture based on a cache hit state for identifying false security dependency conflicts. Background technique [0002] Speculative execution is one of the basic performance optimization measures to improve instruction parallelism in high-performance processors. However, the disclosure of the "Specter" class vulnerability reveals that there are security risks in the speculative execution technology in the existing high-performance processors. In different application scenarios from mobile to cloud, almost all commercial high-performance processors face the risk of being attacked by attackers to steal sensitive information within a wrongly speculated window period. [0003] The generation of "ghost" vulnerabilities depends on two points. 1) The processor uses speculative execution to reduce the performance loss cau...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F21/57G06F9/30G06F9/38
CPCG06F21/577G06F9/30145G06F9/3867
Inventor 侯锐孟丹李沛南赵路坦
Owner INST OF INFORMATION ENG CHINESE ACAD OF SCI
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