Ultrahigh-speed SPI interface implementation device and method
A technology of SPI interface and implementation method, which is applied in the direction of electrical components, automatic power control, instruments, etc., can solve the problem that the signal delay cannot be ignored, and achieve the effect of accurate test and accurate delay time
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Embodiment 1
[0033] Such as figure 1 Shown, the present invention comprises a kind of super high-speed SPI interface realization method, comprises the following steps:
[0034] Step 1: The master device configures the phase-locked loop module according to the local clock module, generates the first SPI receiving reference reference clock, and the SPI sending reference reference clock, and sets the first sampling clock and configures multiple clocks according to the first SPI receiving reference reference clock. delay sample time value;
[0035] Optionally, as in figure 2 As shown, the master device configures the phase-locked loop module according to the local clock module to generate the SPI transmission reference reference clock and the SPI reception reference reference clock respectively. For example, the SPI transmission reference reference clock can be selected as: ref_clk_mosi=200MHz, and the SPI reception reference reference clock is :ref_clk_miso=200MHz. The SPI sending referen...
Embodiment 2
[0049] The present invention also includes a kind of ultra-high-speed SPI interface realization device, comprising:
[0050] Clock setting module, the clock setting module includes a local clock module and a phase-locked loop module, the master device configures the phase-locked loop module according to the local clock module, generates the first SPI receiving reference reference clock, SPI sends the reference reference clock, and receives the reference reference clock according to the SPI setting the first sampling clock with reference to the reference clock;
[0051] Delayed sampling time setting module, the delayed sampling time setting module includes configuring a plurality of delayed sampling time values;
[0052] In the sampling module, after the master device sends data to the slave device, it determines the corresponding start sampling timing according to the first SPI receiving reference reference clock and each configured delay sampling time value, and uses the firs...
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