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A Capacitor Array Structure Suitable for Successive Approximation Analog-to-Digital Converter

A successive approximation type, analog-to-digital converter technology, applied in analog-to-digital conversion, code conversion, instruments, etc., can solve the problems of consumption area and power consumption, and achieve the effect of simple design

Active Publication Date: 2021-09-07
王国兴
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Literature [2] discloses a 1.5-bit / cycle capacitor array structure, which uses two special level shifters (Level Shifter) to move the reference level up and down, thus obtaining 1.5-bit conversion results per cycle; however, this solution requires the design of two level shifters, which also consumes additional area and power consumption

Method used

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  • A Capacitor Array Structure Suitable for Successive Approximation Analog-to-Digital Converter
  • A Capacitor Array Structure Suitable for Successive Approximation Analog-to-Digital Converter
  • A Capacitor Array Structure Suitable for Successive Approximation Analog-to-Digital Converter

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Embodiment 1

[0028] This embodiment implements a capacitor array structure with 2.5 bits per cycle suitable for successive approximation analog-to-digital converters. In this embodiment, the structure and working principle of the novel capacitor array structure for converting 2.5-bit / cycle are taken as an example in detail.

[0029] figure 1 It is a structural schematic diagram of a capacitor array with 2.5 bits per cycle suitable for successive approximation analog-to-digital converters. as attached figure 1 As shown, the overall structure of a new type of 2.5-bit / cycle capacitor array is shown. Among them, VIP and VIN represent the positive terminal and negative terminal input respectively, VCM represents the common mode level, VR represents the reference voltage, GND represents ground, VR / 2 represents half of the reference voltage, VP1 and VN1 represent the first pair of differential The level of the upper plate of the positive capacitor array (P array) and the negative capacitor (N ...

Embodiment 2

[0035] This embodiment implements a capacitance array structure of 1.5 bits per cycle suitable for successive approximation analog-to-digital converters. The capacitor array structure of 1.5-bit / cycle in this embodiment is applicable to the design of successive approximation analog-to-digital converters that have low requirements on conversion rate but high requirements on power consumption and area.

[0036] Figure 4 It is a structural schematic diagram of a 1.5-bit capacitor array per cycle suitable for successive approximation analog-to-digital converters. as attached Figure 4 As shown, the capacitor array structure only needs a differential capacitor array and two comparators with their own input bias voltages to achieve 1.5-bit results per cycle. Other structures and working principles of this embodiment are the same as those of Embodiment 1.

Embodiment 3

[0038] This embodiment implements a capacitor array structure with 3.5 bits per cycle suitable for successive approximation analog-to-digital converters. The structure of a 3.5-bit / cycle capacitor array in this embodiment is applicable to the design of a successive approximation analog-to-digital converter that requires high conversion rate but low power consumption and area.

[0039] Figure 5 It is a structural schematic diagram of a capacitor array with 3.5 bits per cycle suitable for successive approximation analog-to-digital converters. as attached Figure 4 As shown, the capacitor array structure requires five differential capacitor arrays and ten comparators with their own input bias voltages (only two of the differential capacitor arrays are shown in the figure, because the structure of the capacitor arrays is the same, and the remaining three are in the figure omitted in), a result of three point five bits (3.5-bit) per cycle can be achieved. Other structures and w...

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Abstract

The invention relates to a capacitor array structure suitable for successive approximation analog-to-digital converters, which converts N.5 bits per cycle, and the structure includes 2×(N-0.5) pairs of differential capacitor arrays and 2×(N-0.5) pairs of switches Array, 4×(N‑0.5) comparators with intentional input deviation, and digital control logic; the positive input and negative input of the above input signal are connected to the above 2×(N‑0.5) pair differential capacitor array to sample the input signal; the above 2×(N-0.5) pairs of differential capacitor arrays generate 2×(N-0.5) reference voltages according to the connected reference voltage; the above-mentioned 4×(N-0.5) with intentional input deviation The comparator is used to expand the above 2×(N-0.5) reference voltages into 4×(N-0.5) reference voltages, the above digital control logic is based on the above 4×(N-0.5) comparators with intentional input deviation The comparison results of the above-mentioned 2×(N-0.5) pairs of switch arrays are used to control the above-mentioned 2×(N-0.5) pairs of differential capacitor arrays to switch, and the above-mentioned input signals are sampled and compared, and N.5 bits are obtained in one conversion cycle Digital signal. The beneficial effect is to increase the conversion rate of the successive approximation analog-to-digital converter.

Description

【Technical field】 [0001] The invention relates to the technical field of electronic circuits, in particular to a capacitor array structure suitable for successive approximation analog-to-digital converters. 【Background technique】 [0002] Successive approximation analog-to-digital converter, SAR is the abbreviation of successive approximation register in English. In each conversion process, by traversing all quantized values ​​and converting them into analog values, the input signal is compared with it one by one, and finally the output signal is obtained. Digital signal. SAR-ADC converter is composed of: sample and hold circuit, DAC, comparator, successive approximation register, timing and other control circuits, the core is DAC and comparator. [0003] The bootstrap circuit is also called a boost circuit. It uses electronic components such as a bootstrap boost transistor and a bootstrap boost capacitor to superimpose the capacitor discharge voltage and the power supply v...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/38
CPCH03M1/38
Inventor 王国兴赵健罗京
Owner 王国兴