Clock phase shift circuit capable of configuring resolution

Abstract

The invention discloses a clock phase shift circuit capable of configuring resolution, relating to the field of electronic circuits. The clock phase shift circuit receives two paths of differential input clock pairs with a predetermined phase difference through two groups of differential pair transistors; the two groups of differential pair transistors are respectively provided with current by twocurrent modules; each current module can output a plurality of levels of currents with different magnitudes, and the sum of the currents output by the two current modules is fixed; different clock phase shifts can be realized by adjusting the currents output by the two current modules; different phase shift resolutions can be realized by adjusting the predetermined phase difference between the two paths of differential input clock pairs and / or the levels of different currents which can be output by each current module. The phase shift resolution ratio can be flexibly configured, the degree offreedom is higher, the clock phase shift circuit can be suitable for more application scenes, the phase shift resolution ratio is slightly influenced by device characteristics, and the higher phase shift resolution ratio can be realized.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to a clock phase shift circuit with configurable resolution. Background technique [0002] As the operating frequency of the electronic system becomes higher and higher, the phase requirements of the system clock become more and more stringent. In common clock phase shift technologies such as DLL and PLL, it is easy to implement 45°, 90°, 180° and other clock phase shift versions. If you want a finer phase shift, generally use such as figure 1 The delay chain structure DELAY_LINE shown, the delay chain connects some clock delay units (BUF) in series, selects different delay chain nodes through CFG_CTRL, and outputs CLKOUT after different degrees of phase shift on the input clock CLKIN. The minimum unit of the phase shift is The delay of a clock delay unit (BUF), but the delay of a clock delay unit (BUF) is generally tens or hundreds of picoseconds (ps), so the resolution of phas...

AI Technical Summary

Problems solved by technology

If you want a finer phase shift, generally use such as figure 1 The delay chain structure DELAY_LINE shown, the delay chain connects some clock delay units (BUF) in series, selects different delay chain nodes through CFG_CTRL, and outputs CLKOUT after different degrees of phase shift on the input clock CLKIN. The minimum unit of the phase shift is The delay of a clock delay unit (BUF), but the delay of a clock delay unit (BUF) is generally tens or hundreds of picoseconds (ps), so the resolution of phase shifting the clock using the delay chain structure is fixed as Tens, hundreds of picoseconds (ps), low flexibility, and cannot meet higher precision resolution requirements

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