Logic encryption defense method based on key gate position selection

Abstract

The invention relates to a logic encryption defense method based on key gate position selection. The method mainly comprises two parts: data preprocessing and a key gate position encryption algorithm.Specifically, in the encryption process, the positions of the secret key doors are marked in a data preprocessing mode, paths with too long delay are removed, and then a two-stage encryption algorithm is adopted for implanting the positions of the secret key doors and a main guide door. Finally, the Hamming distance and an area overhead are calculated to evaluate the security standard of the encrypted circuit. According to the method, the gate-level netlist encryption effect can be improved; the Hamming distance is greater than 50% through a dominant gate implantation algorithm; the output ambiguity is maximized, the security protection circuit is simple in structure, can resist secret key sensitization attacks, simultaneously reduces area overhead, comprehensively improves security evaluation requirements of logic encryption, reduces problems of IC theft and IP piracy in a chip design stage, and can effectively prevent design information from being maliciously stolen, so that the security protection circuit can be universally applied to logic encryption, and has relatively strong practicability.

Description

technical field [0001] The invention discloses a logic encryption defense method based on key gate position selection. Specifically, in the chip design process, the IP core provided by the third party is integrated into a gate-level netlist circuit. In the gate-level netlist circuit, for the determination of the position of the key gate and the analysis of the critical timing path, additional The logic gate performs netlist encryption. During the process, a corresponding strong interference encryption algorithm is used to perform pre-data processing on the combination position of the key gate. When all data processing is completed, the encryption is realized by two-stage encryption and verification of its Hamming distance. Netlist generation. Background technique [0002] As the complexity and cost of chip design time continue to increase, the design of integrated circuits has gradually shifted to the development of global foundries, outsourcing the process of IC manufactur...

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Problems solved by technology

[0005] In the process of chip design, a logical encryption defense method based on key gate position selection is provided to solve the problem that the encryption scheme of the IP core in the current design stage is difficult to keep the key bit anti-sensitization and high Hamming distance at the same time. The proposed algorithm Not only shortens the running time, but also keeps the area overhead within the security evaluation standard of logical encryption, comprehensively improving the existing security evaluation requirements of logical encryption

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