CPU instruction protection method and system suitable for function and information security chip

Abstract

The invention provides a CPU instruction protection method and system suitable for a function and information security chip. According to the invention, a hash function is utilized to generate an encoding random value and a corresponding decoding random value, and the encoding random value and the original instruction or the encoding instruction value are utilized to perform encoding operation ordecoding operation, so that recoding and decoding of an instruction are correspondingly realized. The output of each round of hash function comprises the information of each previous round of instruction, so that an error in any step will influence all subsequent encoding and decoding processes. Therefore, the encoding random value and the decoding random value among the instructions have corresponding continuity, the exception occurring in any step can be continued to the subsequent steps, so that the detection of the function security and the information security of a chip is realized, the instructions can be recoded and compared after being executed, and the function security and the information security of the CPU instruction storage, reading, decoding and execution processes are protected.

Description

technical field [0001] The invention relates to the technical field of chip security, in particular to a CPU instruction protection method and system suitable for function and information security chips. Background technique [0002] CPU (central processing unit, central processing unit) is the computing and control core of the computer system. CPU instructions are the instructions and commands to direct the machine to work. The program is a series of instructions arranged in a certain order. The process of executing the program is the working process of the computer. . [0003] At present, most CPUs need to go through a series of processes of instruction storage, reading, decoding, and execution to execute instructions. Each step in these processes has a certain probability of encountering random errors, which can lead to functional safety issues. During the operation of the equipment, there are also information security issues caused by hackers. Therefore, the CPU instr...

AI Technical Summary

Problems solved by technology

However, the existing protection methods cannot detect and locate random errors generated during instruction storage, reading, decoding, and execution.

In the existing way, random errors will only be executed directly with the reading, decoding, and execution of instructions, resulting in erroneous behavior in the system

Existing protection mechanisms cannot actively detect hacker attacks, and information security is also difficult to guarantee

[0005] CPU technology and its instruction architecture and compiler technologies are developing rapidly, and the protection technology of CPU and its instructions is also constantly being updated. However, since chips that support functional safety and information security protection are required at the same time, how to protect the CPU and its instructions There is currently no mature technology to learn from the system approach

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