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A test structure and test method of sot-mram

A technology of SOT-MRAM and test structure, applied in the field of test structure of SOT-MRAM, can solve the problems of large area, long test time, large test error, etc.

Active Publication Date: 2022-06-24
ZHEJIANG HIKSTOR TECHOGY CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantages of the aforementioned test methods are: a large number of individual devices require a large test unit (testkey) area, long test time, and statistical data contain wafer (wafer) level process uniformity information, which makes further analysis difficult
In the case of limited precision of the machine, the parallel test method can not greatly improve the test efficiency. In addition, if the device A short circuit (short) occurs, the test structure will not be used

Method used

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  • A test structure and test method of sot-mram
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  • A test structure and test method of sot-mram

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] refer to figure 1 , figure 2 and image 3 , the excitation circuit includes two second test electrodes 32 (denoted by electrode D and electrode E as two second test electrodes 32), and the above-mentioned two second test electrodes 32 are used to provide inversion for the n spin-orbit torque supply lines 20 current. Both ends of each spin-orbit torque providing wire 20 are respectively connected in series with the two second test electrodes 32 , and any two spin-orbit torque providing wires 20 are connected in parallel. The excitation circuit also includes two control switches 40 connected in series at both ends of each spin-orbit torque supply line 20 and used to control whether the two second test electrodes 32 and each spin-orbit torque supply line 20 are open or closed . By using n spin-orbit torque supply lines 20 connected in parallel, and a control switch 40 is provided at both ends of each spin-orbit torque supply line 20 . Therefore, when the n magnetic t...

Embodiment 2

[0043] refer to Figure 4 , Figure 5 and Image 6 , a series connection between the spin-orbit moment-providing wires 20 can also be used. Specifically, as Figure 4 As shown, between any two adjacent spin-orbit moment magnetic storage bits, the spin-orbit moment supply line 20 in one of the spin-orbit moment magnetic storage bits and the other spin-orbit moment magnetic storage bit The spin-orbit moment in provides lines 20 connected in series. The two first test electrodes 31 ( Figure 4 , Figure 5 , Image 6 The electrodes A and C in the two first test electrodes 31) are also connected in series with the two spin-orbit torque supply lines 20 located at the head and tail ends of the n spin-orbit torque supply lines 20, respectively, so as to provide n spin-orbit moment supply lines 20 in series. The track moment supply line 20 supplies the inversion current. The excitation circuit includes a control switch 40 disposed between any two adjacent spin-orbit torque supp...

Embodiment 3

[0051] Some of the n spin-orbit moment supply lines 20 may be connected in parallel, and some may be connected in series. The specific arrangement of the parallel connection of a plurality of spin-orbit moment supply lines 20 is the same as that in Embodiment 1, and the specific arrangement of the serial connection of a plurality of spin-orbit moment supply lines 20 is the same as that of Embodiment 2. It is not repeated here.

[0052] In addition, it should be noted that when specifically determining whether the n spin-orbit moment providing wires 20 are connected in series or in parallel, it can be determined according to the number of spin-orbit moment providing wires 20. When the number of orbital moment providing wires 20 is large, a parallel connection can be adopted, so as to ensure that the excitation voltages on each spin-orbit moment providing wire 20 are equal. When the number of spin-orbit torque supply lines 20 is small, a series connection can be adopted, thereb...

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Abstract

The invention provides a SOT-MRAM test structure and a test method thereof. The test structure includes n spin-orbit moment magnetic storage bits connected in series from head to tail. Each spin-orbit moment magnetic storage bit includes a spin-orbit moment supply line and a magnetic tunnel junction arranged on the spin-orbit moment supply line; between two adjacent spin-orbit moment magnetic storage bits, one of the A magnetic tunnel junction provides a line connection with another spin-orbit moment in the junction. It also includes an excitation circuit for exciting n magnetic tunnel junctions, and two first test electrodes, and the two first test electrodes are respectively connected to the two spin-orbit electrodes located at the first and last ends of the n spin-orbit moment magnetic storage bits. Magnetic moment storage bit connection. The test structure is simplified and the total area of ​​the test device is reduced by arranging n spin-orbit moment magnetic storage bits connected in series head to tail, the first test electrode, and the excitation circuit. Simultaneously test a large number of devices to improve test efficiency.

Description

technical field [0001] The invention relates to the technical field of semiconductors, and in particular, to a test structure and a test method of a SOT-MRAM. Background technique [0002] Magnetic random access memory SOT (Spin Orbit Torque, spin-orbit torque) MRAM (Magnetic Random Access Memory, a non-volatile magnetic random access memory), which has developed rapidly in recent years, has excellent characteristics. It overcomes the shortcomings of SRAM (Static Random-Access Memory, static random access memory), which has a large area and large leakage after the size is reduced; it also overcomes the need for DRAM (Dynamic Random Access Memory, dynamic random access memory) to keep data refresh , the disadvantage of large power consumption. Compared with Flash memory (flash memory), magnetic random access memory SOT MRAM has several orders of magnitude superior read and write time and read and write times. [0003] At present, the core storage unit of the MRAM memory gen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/50
CPCG11C29/50008G11C2029/5004G11C2029/5006
Inventor 哀立波王明王璐
Owner ZHEJIANG HIKSTOR TECHOGY CO LTD