Three-dimensional memory structure and its preparation method
A memory, three-dimensional technology, applied in semiconductor devices, electrical solid-state devices, electrical components, etc., can solve problems such as functional sidewall damage, and achieve the effects of low production cost, improved product yield and reliability, and simple process
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Embodiment 1
[0155] Figure 5 A schematic flowchart showing a method for preparing a three-dimensional memory structure according to an embodiment of the present invention. The preparation method of the three-dimensional memory structure includes the following steps:
[0156] Step S10, providing a semiconductor substrate;
[0157] Step S20, forming a stacked structure on the semiconductor substrate, wherein channel holes are formed in the stacked structure, wherein the stacked structure includes alternately stacked first insulating dielectric layers and first sacrificial layers, so The channel hole penetrates the stacked structure along the thickness direction of the stacked structure and extends into the semiconductor substrate;
[0158] Step S30, filling the bottom of the channel hole with a second sacrificial layer;
[0159] Step S40, forming functional sidewalls and a channel layer in the channel hole filled with the second sacrificial layer;
[0160] Step S50, replacing all the fi...
Embodiment 2
[0190] see Figure 18 The present invention also provides a three-dimensional memory structure prepared by the method for preparing a three-dimensional memory structure described in Embodiment 1, comprising a semiconductor substrate 200, a gate stack structure 221, a bottom connection layer 228, functional sidewalls 212 and a channel layer 213. It should be noted that, in this embodiment, the orientation is described with reference to when the semiconductor substrate 200 is at the bottom. It should be noted that, in this embodiment, the semiconductor substrate 200, the gate stack structure 221, the bottom connection layer 228, and the functional sidewall 212 are detailed in terms of the formation process of the channel layer 213. See the description of relevant parts of Embodiment 1, and details are not repeated in this embodiment.
[0191] In this embodiment, the semiconductor substrate 200 can be selected according to the actual requirements of the device, and the semicond...
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