Three-dimensional memory structure and its preparation method
A memory, three-dimensional technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of ONO film damage, the incomplete alignment of the upper and lower channel holes, and the influence of the electrical properties of the storage unit, so as to improve the quality of the product. The effect of rate and reliability
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0151] see Figure 14 , the present embodiment provides a three-dimensional memory structure, the three-dimensional memory structure includes a first chip 200, the first chip 200 as a memory array chip (Array Wafer), including a bottom conductive layer, a gate stack structure 202, an epitaxial Layer 227 , vertical channel structure and interconnect structure 221 . It should be noted that, in this implementation, for convenience of discussion, the side of the bottom conductive layer of the first chip 200 is defined as the bottom, and the side of the first chip 200 away from the bottom conductive layer is defined as the bottom. One side of is defined as the top.
[0152] see Figure 14 , in this embodiment, the gate stack structure 202 is formed on the bottom conductive layer, a channel hole (not marked) is formed in the gate stack structure 202, and the channel hole penetrates the gate pole stack structure 202; the epitaxial layer 227 is formed at the bottom of the channel h...
Embodiment 2
[0172] image 3 A flow chart of the preparation of the three-dimensional memory structure of this embodiment is shown. see image 3 , the preparation method of the three-dimensional memory structure includes:
[0173] Step S10, providing a first chip 200, the first chip 200 comprising a semiconductor substrate 201, a gate stack structure 202, an epitaxial layer 227 and a vertical channel structure;
[0174] Step S20, performing a first thinning treatment on the surface of the semiconductor substrate 201 away from the gate stack structure 202 until the epitaxial layer 227 is exposed;
[0175] Step S30, forming a through-hole 220 in the epitaxial layer 227 that sequentially penetrates the bottom of the epitaxial layer 227 and the functional sidewall 211, so as to expose the channel layer 212 of the vertical channel structure;
[0176] Step S40, forming an interconnect material layer 2210 on the surface of the first chip 200 on which the through hole 220 is formed, the interco...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More