Stress compensation and relief in bonded wafers

Abstract

Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in thewafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not atthe predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, the subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.

Description

Background technique [0001] As transistor technology improves, higher operating frequencies become available. The functions of these integrated circuits (ICs) have been improved, and various silicon-based System-on-Chip (SOC) or sensor chip assembly / array (Sensor Chip Assembly / Array, SCA) have been proven. These devices can be manufactured by bonding two wafers together to obtain these functions. However, bonded wafer devices can result in bonded wafer pairs with significantly high stress in the structure. [0002] As we all know, the bonded wafer devices are cut into small pieces to obtain individual dies. Unfortunately, the stress in the bonded wafer device causes a single die to have unacceptable bending parameters, that is, the flatness of the die is not enough to meet the expected performance requirements. [0003] Therefore, there is a need for a method of obtaining individual dies having acceptable (ie, predetermined) flatness characteristics from bonded wafer devices. Su...

AI Technical Summary

Problems solved by technology

Unfortunately, however, the stress in the bonded wafer device results in an individual die with unacceptable bow parameters, i.e., the die is not flat enough to meet expected performance requirements

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