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Multi-stage merging and sorting method based on FPGA implementation

A sorting method and a technology for realizing the method, which are applied in the field of computer communication and can solve the problems of low processing speed and difficulty in high-frequency operation.

Active Publication Date: 2020-08-21
SHANGHAI UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that the existing FPGA-based merge sorting method has low processing speed and is difficult to operate at high frequency as the number of sorts increases. The multi-level merge sorting method implemented by FPGA makes the number of gate levels constant when the number of merge sorts increases, and can realize sorting queues of any length for merging

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  • Multi-stage merging and sorting method based on FPGA implementation
  • Multi-stage merging and sorting method based on FPGA implementation
  • Multi-stage merging and sorting method based on FPGA implementation

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Embodiment 1

[0057] Such as image 3 Therefore, this embodiment takes the secondary merge sorting of four sets of data in the database as an example, and the queue to be sorted 1_A, the queue to be sorted 1_B, the queue to be sorted 2_A, and the queue to be sorted 2_B are merged and sorted in ascending order.

[0058] 1. When the first level is merged: the queue to be sorted 1_A contains the data to be sorted data_A{1,2,3}, the sorted data flags last_A{1,0,0} and none_A{0,0,0}; the queue to be sorted 1_B contains data to be sorted data_B{4,5}, sorted data flags last_B{1,0} and none_B{0,0};

[0059] (1) It is detected that none_A and none_B corresponding to data_A:3 and data_B:5 are both low level, that is, both queue 1_A to be sorted and queue 1_B to be sorted are valid data;

[0060] (2) Compare data_A to be sorted with data B to be sorted, data_A:3data_A:3, then data_B :4 is written into the sorting result;

[0061] (3) It is detected that the flag bit last_B corresponding to data_B:4...

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Abstract

The invention discloses a multi-stage merging and sorting method based on FPGA (Field Programmable Gate Array), which comprises the following steps: step 1, detecting a plurality of 2 merging and sorting modules, with each 2 merging and sorting module comprising to-be-sorted data A and to-be-sorted data B; step 2, merging and sorting the plurality of 2 merging and sorting modules respectively, andoutputting sorting results; and step 3, taking the arrangement result as a to-be-sorted next-level queue, entering a next-level merging and sorting module, and repeating the step 1 and the step 2 until a final arrangement result is output. When the merging and sorting number is increased, the gate stage number is constant, and merging of sorting queues of any length can be achieved.

Description

technical field [0001] The invention relates to the field of computer communication, in particular to a multi-level merge and sort method realized based on FPGA. Background technique [0002] Sorting is a very important class of problems in the field of computer applications, with extensive research and applications. For example, sorting algorithms are widely used in data processing, databases, data compression, distributed computing, image processing, and computer graphics. The mainstream sorting algorithms are often developed based on the CPU, such as bubble sorting, insertion sorting, binary tree sorting, quick sorting, etc. In order to fully improve the efficiency of solving sorting problems and improve the speed of algorithm operation, researchers have designed various algorithms for different problems. In addition to this kind of sorting algorithm, many parallel sorting algorithms have been designed in combination with the parallelism characteristics of the sorting pr...

Claims

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Application Information

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IPC IPC(8): G06F7/24
CPCG06F7/24Y02D10/00
Inventor 张俊杰田森曹炳尧庄耀宇杨丹张倩武陈健宋英雄李迎春
Owner SHANGHAI UNIV
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