Chip packaging method and chip structure

Abstract

The invention discloses a chip packaging method and a chip structure. The chip packaging method comprises the steps: providing a first wafer provided with a plurality of chips; forming a rewiring layer on the surface of the first wafer; forming a metal column structure on the surface of the rewiring layer to form a second wafer; cutting the second wafer to form at least one first sub-wafer and atleast one second sub-wafer; carrying out lead wire bonding packaging on the first sub-wafer; and performing flip-chip packaging on the second sub-wafer. According to the chip packaging method providedby the invention, the number of wafers can be reduced, so that the cost can be saved, and the efficiency can also be improved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a chip packaging method and a chip structure. Background technique [0002] With the increasing integration of electronic devices, a stacked semiconductor packaging technology (Package on Package, PoP) and a chip stacked packaging technology (Stacked Die Package) have been proposed in the field of semiconductor packaging. In this type of package, multiple packages or bare chips are overlapped in the height direction to reduce the footprint of the package. [0003] Currently, chip stacking PoPs generally adopt wire bonding (Wire Bond, WB) or flip chip (Flip Chip, FC) packaging. [0004] Wire bonding (WB): using thin metal wires, heat, pressure, and ultrasonic energy are used to closely bond the metal wires to the chip pads and substrate pads to achieve electrical interconnection between chips and substrates and information exchange between chips , widely used in RF modules...

AI Technical Summary

Problems solved by technology

[0006] Generally, WB packaging or FC packaging is used, but sometimes it is necessary to use two packaging methods at the same time. For example, a chip mainly packaged in FC also needs to be packaged in WB. According to the current traditional technology, the chip is processed (fab out) after initial molding, a batch of WB packaging (requires corresponding wafers), and another batch of copper pillars (pillar) and FC packaging (also requires corresponding wafers), it can be seen that WB packaging and FC Packaging needs to be carried out separately, and each requires its own wafer. For chips that are mainly packaged in FC, an independent wafer must also be used for WB packaging, which will increase the number of wafers and increase the cost.

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